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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. H8/3502 HD6433502 Hardware Manual 3/13/03 Notice When using this document, keep the following in mind: 1. 2. 3. This document may, wholly or partially, be subject to change without notice. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. 4. 5. 6. Preface The H8/3502 is a high-performance single-chip microcomputer ideally suited for embedded control applications. The chip is built around a high-speed H8/300 CPU core. On-chip supporting modules include 16-kbyte ROM, 512-byte RAM, three types of timers, a serial communication interface, host interface, and I/O ports, for easy implementation of compact, high-performance control systems. Development tools that support the functionally higher-end H8/3217 Series should be used for H8/3502 program development. The H8/3502 is also available as a ZTATTM (Zero Turn-Around Time) version of the functionally higher-end H8/3214. This version enables the user to respond quickly and flexibly to changing application system specifications and the demands of the transition from initial to full-fledged volume production. There are a number of differences between the H8/3502 and the functionally higher-end H8/3217 Series. In terms of functions, the H8/3502 is available in only one ROM/RAM configuration, has a maximum operating frequency of 10 MHz, and does not offer a guaranteed current dissipation figure in standby mode, one of its power-down states. The H8/3502 single-chip microcomputer is intended for consumer applications. If the user requires a ZTATTM version, larger ROM/RAM capacity, processing at a maximum 16 MHz, significant power reduction in standby mode for portable systems, etc., or the high reliability essential for automotive or industrial applications, the H8/3217 Series should be used. This manual describes the H8/3502 hardware. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set, and to the H8/3217 Series Hardware Manual for details of higher-end products, including ZTATTM versions. Note: ZTAT is a trademark of Hitachi, Ltd. Contents Section 1 Overview ............................................................................................................ 1.1 1.2 1.3 Overview .......................................................................................................................... Block Diagram ................................................................................................................. Pin Assignments and Functions........................................................................................ 1.3.1 Pin Arrangement ................................................................................................. 1.3.2 Pin Functions....................................................................................................... 1 1 4 5 5 7 Section 2 CPU...................................................................................................................... 15 2.1 Overview .......................................................................................................................... 2.1.1 Features ............................................................................................................... 2.1.2 Address Space ..................................................................................................... 2.1.3 Register Configuration ........................................................................................ Register Descriptions........................................................................................................ 2.2.1 General Registers ................................................................................................ 2.2.2 Control Registers................................................................................................. 2.2.3 Initial Register Values ......................................................................................... Data Formats .................................................................................................................... 2.3.1 Data Formats in General Registers...................................................................... 2.3.2 Memory Data Formats ........................................................................................ Addressing Modes............................................................................................................ 2.4.1 Addressing Modes............................................................................................... 2.4.2 Effective Address Calculation............................................................................. Instruction Set .................................................................................................................. 2.5.1 Data Transfer Instructions ................................................................................... 2.5.2 Arithmetic Operations ......................................................................................... 2.5.3 Logic Operations ................................................................................................. 2.5.4 Shift Operations .................................................................................................. 2.5.5 Bit Manipulations................................................................................................ 2.5.6 Branching Instructions ........................................................................................ 2.5.7 System Control Instructions................................................................................ 2.5.8 Block Data Transfer Instruction.......................................................................... CPU States........................................................................................................................ 2.6.1 Overview ............................................................................................................. 2.6.2 Program Execution State ..................................................................................... 2.6.3 Exception-Handling State ................................................................................... 2.6.4 Power-Down State .............................................................................................. Access Timing and Bus Cycle.......................................................................................... 2.7.1 Access to On-Chip Memory (RAM and ROM).................................................. 2.7.2 Access to On-Chip Register Field and External Devices.................................... 15 15 16 16 17 17 17 18 19 20 21 22 22 23 27 29 31 32 32 34 39 41 42 44 44 45 45 45 46 46 49 2.2 2.3 2.4 2.5 2.6 2.7 Section 3 MCU Operating Modes and Address Space............................................ 53 3.1 Overview .......................................................................................................................... 53 3.1.1 Operating Modes ................................................................................................. 53 3.1.2 Mode and System Control Registers ................................................................... 53 System Control Register (SYSCR) .................................................................................. 54 Mode Control Register (MDCR)...................................................................................... 56 Mode Descriptions............................................................................................................ 56 Address Space Maps for Each Operating Mode .............................................................. 57 3.2 3.3 3.4 3.5 Section 4 Exception Handling......................................................................................... 59 4.1 4.2 Overview .......................................................................................................................... Reset ................................................................................................................................. 4.2.1 Overview ............................................................................................................. 4.2.2 Reset Sequence.................................................................................................... 4.2.3 Disabling of Interrupts after Reset ...................................................................... Interrupts .......................................................................................................................... 4.3.1 Overview ............................................................................................................. 4.3.2 Interrupt-Related Registers ................................................................................. 4.3.3 External Interrupts............................................................................................... 4.3.4 Internal Interrupts................................................................................................ 4.3.5 Interrupt Handling ............................................................................................... 4.3.6 Interrupt Response Time ..................................................................................... 4.3.7 Precaution............................................................................................................ Note on Stack Handling.................................................................................................... Notes on the Use of Key-Sense Interrupts ....................................................................... 59 59 59 60 63 63 63 65 68 69 69 75 75 76 77 4.3 4.4 4.5 Section 5 Wait-State Controller...................................................................................... 79 5.1 Overview .......................................................................................................................... 79 5.1.1 Features ............................................................................................................... 79 5.1.2 Block Diagram .................................................................................................... 79 5.1.3 Input/Output Pins ................................................................................................ 80 5.1.4 Register Configuration ........................................................................................ 80 Register Description ......................................................................................................... 80 5.2.1 Wait-State Control Register (WSCR) ................................................................. 80 Wait Modes ...................................................................................................................... 82 5.2 5.3 Section 6 Clock Pulse Generator.................................................................................... 85 6.1 Overview .......................................................................................................................... 85 6.1.1 Block Diagram .................................................................................................... 85 6.1.2 Wait-State Control Register (WSCR) ................................................................. 86 Oscillator Circuit .............................................................................................................. 87 Duty Adjustment Circuit .................................................................................................. 93 Prescaler ........................................................................................................................... 93 6.2 6.3 6.4 Section 7 I/O Ports.............................................................................................................. 95 7.1 7.2 Overview .......................................................................................................................... Port 1 ................................................................................................................................ 7.2.1 Overview ............................................................................................................. 7.2.2 Register Configuration and Descriptions ............................................................ 7.2.3 Pin Functions in Each Mode ............................................................................... 7.2.4 MOS Input Pull-Ups............................................................................................ Port 2 ................................................................................................................................ 7.3.1 Overview ............................................................................................................. 7.3.2 Register Configuration and Descriptions ............................................................ 7.3.3 Pin Functions in Each Mode ............................................................................... 7.3.4 MOS Input Pull-Ups............................................................................................ Port 3 ................................................................................................................................ 7.4.1 Overview ............................................................................................................. 7.4.2 Register Configuration and Descriptions ............................................................ 7.4.3 Pin Functions in Each Mode ............................................................................... 7.4.4 Input Pull-Up Transistors.................................................................................... Port 4 ................................................................................................................................ 7.5.1 Overview ............................................................................................................. 7.5.2 Register Configuration and Descriptions ............................................................ 7.5.3 Pin Functions....................................................................................................... Port 5 ................................................................................................................................ 7.6.1 Overview ............................................................................................................. 7.6.2 Register Configuration and Descriptions ............................................................ 7.6.3 Pin Functions....................................................................................................... Port 6 ................................................................................................................................ 7.7.1 Overview ............................................................................................................. 7.7.2 Register Configuration and Descriptions............................................................ 7.7.3 Pin Functions....................................................................................................... Port 7 ................................................................................................................................ 7.8.1 Overview ............................................................................................................. 7.8.2 Register Configuration and Descriptions ............................................................ 7.8.3 Pin Functions....................................................................................................... 95 98 98 99 101 103 104 104 105 107 110 111 111 112 114 115 116 116 117 119 122 122 122 124 126 126 127 129 131 131 132 134 7.3 7.4 7.5 7.6 7.7 7.8 Section 8 16-Bit Free-Running Timer .......................................................................... 137 8.1 Overview .......................................................................................................................... 8.1.1 Features ............................................................................................................... 8.1.2 Block Diagram .................................................................................................... 8.1.3 Input and Output Pins.......................................................................................... 8.1.4 Register Configuration ........................................................................................ Register Descriptions........................................................................................................ 8.2.1 Free-Running Counter (FRC)--H'FF92.............................................................. 137 137 138 139 139 140 140 8.2 8.3 8.4 8.5 8.6 8.7 Output Compare Registers A and B (OCRA and OCRB)--H'FF94 and H'FF96................................................................................................................. 8.2.3 Input Capture Register (ICR)--H'FF98.............................................................. 8.2.4 Timer Control Register (TCR)--H'FF90............................................................ 8.2.5 Timer Control/Status Register (TCSR)--H'FF91 ............................................... CPU Interface ................................................................................................................... Operation .......................................................................................................................... 8.4.1 FRC Incrementation Timing ............................................................................... 8.4.2 Output Compare Timing ..................................................................................... 8.4.3 FRC Clear Timing............................................................................................... 8.4.4 Input Capture Timing.......................................................................................... 8.4.5 Timing of Input Capture Flag (ICF) Setting ....................................................... 8.4.6 Setting of FRC Overflow Flag (OVF) ................................................................ Interrupts .......................................................................................................................... Sample Application .......................................................................................................... Application Notes............................................................................................................. 8.2.2 140 141 142 144 147 150 150 152 152 153 154 154 155 155 156 Section 9 8-Bit Timers ...................................................................................................... 161 9.1 Overview .......................................................................................................................... 161 9.1.1 Features ............................................................................................................... 161 9.1.2 Block Diagram .................................................................................................... 162 9.1.3 Input and Output Pins.......................................................................................... 163 9.1.4 Register Configuration ........................................................................................ 163 Register Descriptions........................................................................................................ 164 9.2.1 Timer Counter (TCNT)--H'FFCC (TMR0), H'FFD4 (TMR1), H'FF9E (TMRX) ................................................................................................. 164 9.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1), H'FF9C and H'FF9D (TMRX)................................................................................................. 164 9.2.3 Timer Control Register (TCR)--H'FFC8 (TMR0), H'FFD0 (TMR1), H'FF9A (TMRX)................................................................................................. 165 9.2.4 Timer Control/Status Register (TCSR)--H'FFC9 (TMR0), H'FFD1 (TMR1), H'FF9B (TMRX) ................................................................................................. 168 9.2.5 Serial/Timer Control Register (STCR) ............................................................... 171 Operation .......................................................................................................................... 172 9.3.1 TCNT Incrementation Timing ............................................................................ 172 9.3.2 Compare Match Timing ...................................................................................... 174 9.3.3 External Reset of TCNT...................................................................................... 176 9.3.4 Setting of TCSR Overflow Flag.......................................................................... 176 Interrupts .......................................................................................................................... 177 Sample Application .......................................................................................................... 177 Application Notes............................................................................................................. 178 9.6.1 Contention between TCNT Write and Clear....................................................... 178 9.2 9.3 9.4 9.5 9.6 9.6.2 9.6.3 9.6.4 9.6.5 Contention between TCNT Write and Increment ............................................... Contention between TCOR Write and Compare-Match ..................................... Contention between Compare-Match A and Compare-Match B........................ Incrementation Caused by Changing of Internal Clock Source.......................... 179 180 181 181 Section 10 Watchdog Timer ............................................................................................ 185 10.1 Overview .......................................................................................................................... 10.1.1 Features ............................................................................................................... 10.1.2 Block Diagram .................................................................................................... 10.1.3 Register Configuration ........................................................................................ 10.2 Register Descriptions........................................................................................................ 10.2.1 Timer Counter (TCNT) ....................................................................................... 10.2.2 Timer Control/Status Register (TCSR) ............................................................... 10.2.3 Register Access ................................................................................................... 10.3 Operation .......................................................................................................................... 10.3.1 Watchdog Timer Mode ....................................................................................... 10.3.2 Interval Timer Mode ........................................................................................... 10.3.3 Setting the Overflow Flag ................................................................................... 10.4 Application Notes............................................................................................................. 10.4.1 Contention between TCNT Write and Increment ............................................... 10.4.2 Changing the Clock Select Bits (CKS2 to CKS0) .............................................. 10.4.3 Recovery from Software Standby Mode ............................................................. 185 185 186 186 187 187 187 189 190 190 191 191 192 192 192 192 Section 11 Serial Communication Interface ................................................................ 193 11.1 Overview .......................................................................................................................... 11.1.1 Features ............................................................................................................... 11.1.2 Block Diagram .................................................................................................... 11.1.3 Input and Output Pins.......................................................................................... 11.1.4 Register Configuration ........................................................................................ 11.2 Register Descriptions........................................................................................................ 11.2.1 Receive Shift Register (RSR).............................................................................. 11.2.2 Receive Data Register (RDR) ............................................................................. 11.2.3 Transmit Shift Register (TSR) ............................................................................ 11.2.4 Transmit Data Register (TDR)............................................................................ 11.2.5 Serial Mode Register (SMR)............................................................................... 11.2.6 Serial Control Register (SCR)............................................................................. 11.2.7 Serial Status Register (SSR)................................................................................ 11.2.8 Bit Rate Register (BRR)...................................................................................... 11.2.9 Serial Communication Mode Register (SCMR) ................................................. 11.3 Operation .......................................................................................................................... 11.3.1 Overview ............................................................................................................. 11.3.2 Asynchronous Mode ........................................................................................... 11.3.3 Synchronous Mode.............................................................................................. 193 193 195 196 197 198 198 198 198 199 199 202 205 208 212 213 213 215 229 11.4 Interrupts .......................................................................................................................... 237 11.5 Application Notes............................................................................................................. 237 Section 12 Host Interface.................................................................................................. 241 12.1 Overview .......................................................................................................................... 12.1.1 Block Diagram .................................................................................................... 12.1.2 Input and Output Pins.......................................................................................... 12.1.3 Register Configuration ........................................................................................ 12.2 Register Descriptions........................................................................................................ 12.2.1 System Control Register (SYSCR) ..................................................................... 12.2.2 Host Interface Control Register (HICR) ............................................................. 12.2.3 Input Data Register 1 (IDR1).............................................................................. 12.2.4 Output Data Register 1 (ODR1).......................................................................... 12.2.5 Status Register 1 (STR1)..................................................................................... 12.2.6 Input Data Register 2 (IDR2).............................................................................. 12.2.7 Output Data Register 2 (ODR2).......................................................................... 12.2.8 Status Register 2 (STR2)..................................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Host Interface Operation ..................................................................................... 12.3.2 Control States ...................................................................................................... 12.3.3 A20 Gate .............................................................................................................. 12.4 Interrupts .......................................................................................................................... 12.4.1 IBF1, IBF2 .......................................................................................................... 12.4.2 HIRQ11, HIRQ1, and HIRQ12 ............................................................................. 12.5 Application Note .............................................................................................................. 241 242 243 244 245 245 245 246 247 247 248 249 249 251 251 251 252 255 255 255 256 Section 13 RAM.................................................................................................................. 257 13.1 13.2 13.3 13.4 Overview .......................................................................................................................... Block Diagram.................................................................................................................. RAM Enable Bit (RAME)................................................................................................ Operation .......................................................................................................................... 13.4.1 Expanded Modes (Modes 1 and 2)...................................................................... 13.4.2 Single-Chip Mode (Mode 3) ............................................................................... 257 257 258 258 258 258 Section 14 ROM.................................................................................................................. 259 14.1 Overview .......................................................................................................................... 259 14.1.1 Block Diagram .................................................................................................... 260 Section 15 Power-Down State ........................................................................................ 261 15.1 Overview .......................................................................................................................... 15.1.1 System Control Register (SYSCR) ..................................................................... 15.2 Sleep Mode....................................................................................................................... 15.2.1 Transition to Sleep Mode .................................................................................... 261 262 263 263 15.2.2 Exit from Sleep Mode ......................................................................................... 15.3 Software Standby Mode ................................................................................................... 15.3.1 Transition to Software Standby Mode ................................................................ 15.3.2 Exit from Software Standby Mode...................................................................... 15.3.3 Clock Settling Time for Exit from Software Standby Mode .............................. 15.3.4 Sample Application of Software Standby Mode................................................. 15.3.5 Note on Current Dissipation................................................................................ 15.4 Hardware Standby Mode.................................................................................................. 15.4.1 Transition to Hardware Standby Mode ............................................................... 15.4.2 Recovery from Hardware Standby Mode............................................................ 15.4.3 Timing Relationships .......................................................................................... 263 264 264 264 264 266 266 267 267 267 268 Section 16 Electrical Specifications.............................................................................. 269 16.1 Absolute Maximum Ratings............................................................................................. 16.2 Electrical Characteristics.................................................................................................. 16.2.1 DC Characteristics .............................................................................................. 16.2.2 AC Characteristics .............................................................................................. 16.3 MCU Operational Timing ................................................................................................ 16.3.1 Bus Timing.......................................................................................................... 16.3.2 Control Signal Timing ........................................................................................ 16.3.3 16-Bit Free-Running Timer Timing.................................................................... 16.3.4 8-Bit Timer Timing ............................................................................................. 16.3.5 Serial Communication Interface Timing............................................................. 16.3.6 I/O Port Timing ................................................................................................... 16.3.7 Host Interface Timing ......................................................................................... 16.3.8 External Clock Output Timing............................................................................ 269 269 269 273 278 279 281 283 284 285 286 287 288 Appendix A Instruction Set.............................................................................................. 289 A.1 A.2 A.3 Instruction List.................................................................................................................. 289 Operation Code Map ........................................................................................................ 298 Number of States Required for Execution........................................................................ 300 Appendix B Internal I/O Register .................................................................................. 307 B.1 B.2 Addresses.......................................................................................................................... 307 B.1.1 I/O Registers ......................................................................................................... 307 Function............................................................................................................................ 312 Appendix C I/O Port Block Diagrams.......................................................................... 346 C.1 C.2 C.3 C.4 C.5 Port 1 Block Diagram....................................................................................................... Port 2 Block Diagram....................................................................................................... Port 3 Block Diagram....................................................................................................... Port 4 Block Diagrams ..................................................................................................... Port 5 Block Diagrams ..................................................................................................... 346 347 348 349 355 C.6 C.7 Port 6 Block Diagrams ..................................................................................................... 358 Port 7 Block Diagrams ..................................................................................................... 361 Appendix D Pin States ....................................................................................................... 365 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode.............................................................................................. 367 Appendix F Product Code Lineup ................................................................................. 368 Appendix G Package Dimensions.................................................................................. 369 Section 1 Overview 1.1 Overview The H8/3502 is a series of single-chip microcomputers integrating a CPU core together with a variety of peripheral functions needed in control systems. The H8/300 CPU is a high-speed processor featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. On-chip supporting modules necessary for system configuration include 16-kbyte ROM, 512-byte RAM, three types of timers (16-bit free-running timer, 8-bit timer, and watchdog timer), a serial communication interface (SCI), host interface (HIF), and I/O ports. The H8/3502 can operate in single-chip mode or in two expanded modes, depending on the memory requirements of the application. Development tools that support the functionally higher-end H8/3217 Series should be used for H8/3502 program development. As a ZTATTM version, use the ZTATTM version of the H8/3214. Registers related to higher-level functions should not be accessed in this case. In particular, 1 must not be written in the IICS, IICX1, IICX0, SYNCE, PWCKE, and PWCKS bits in the serial/timer control register (STCR). Note: ZTAT is a trademark of Hitachi, Ltd. Table 1-1 lists the features of the H8/3502. 1 Table 1-1 Feature CPU Features Description General register architecture * Eight 16-bit general registers, or * Sixteen 8-bit general registers High speed * Maximum clock rate: 10 MHz/5 V (o clock) * Add/subtract: 200 ns (10 MHz operation) * Multiply/divide: 1400 ns (10 MHz operation) Concise, streamlined instruction set * All instructions are 2 or 4 bytes long * Register-register arithmetic and logic operations * Register-memory data transfer by MOV instruction Instruction set features * Multiply instruction (8 bits x 8 bits) * Divide instruction (16 bits / 8 bits) * Bit-accumulator instructions * Register-indirect specification of bit positions Memory 16-Bit free-running timer (FRT: 1 channel) 8-bit timer (TMR: 2 channels) Watchdog timer (WDT: 1 channel) * ROM: 16 kbytes * RAM: 512 bytes * One 16-bit free-running counter (also usable for external event counting) * Two compare outputs * One capture input Each channel has: * One 8-bit up-counter (also usable for external event counting) * Two time constant registers * Reset or NMI generation by overflow * Can be switched to interval timer mode 2 Table 1-1 Feature Features (cont) Description * Selection of asynchronous and synchronous modes * Simultaneous transmit and receive (full duplex operation) * On-chip baud rate generator * * * * 8-bit host interface port Three host interrupt requests (HIRQ 1, HIRQ11, HIRQ12) Normal and fast A20 gate output Two register sets (each comprising two data registers and a status register) Serial communication interface (SCI: 2 channels) Host interface (HIF) Keyboard controller I/O ports Interrupts * Controls a matrix keyboard using a keyboard scan with wake-up interrupt and sense port configuration * 53 input/output pins (of which 24 can drive large current loads) * Four external interrupt pins: NMI, IRQ0 to IRQ2 * Eight key-sense interrupt pins: KEYIN0 to KEYIN7 * Twenty-one on-chip interrupt sources * Mode 1: expanded mode with on-chip ROM disabled * Mode 2: expanded mode with on-chip ROM enabled * Mode 3: single-chip mode * Sleep mode * Software standby mode * Hardware standby mode * On-chip clock oscillator Product Name H8/3502 Type Code HD6433502P10 HD6433502F10 Package 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) ROM Mask ROM Operating modes Power-down state Other features Product lineup 3 1.2 Block Diagram Figure 1-1 shows a block diagram of the H8/3502. See table 1-2, Pin Assignments in Each Operating Mode, for differences in the pin functions. EXTAL Clock pulse generator RES MD0 MD1 NMI STBY VCC VCC VSS VSS CPU H8/300 XTAL P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Data bus (low) Data bus (high) Address bus Port 7 Port 3 Port 6 KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/P62/FTOB KEYIN3/P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2 Port 4 P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/P43/TMCI1 HIRQ1/P44/TMO1 HIRQ12/P45/TMRI1 CS2/P46/o GA20/P47 ROM RAM Watchdog timer Host interface P70/KEYIN4 P71/KEYIN5 P72/KEYIN6 P73/KEYIN7 P74/AS/CS1 P75/WR/IOW P76/RD/IOR P77/WAIT/HA0 Port 1 16-bit free-running timer P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 Serial communication interface (2 channels) 8-bit timer (2 channels) (TMR0, TMR1) P30/D0/HDB0 P31/D1/HDB1 P32/D2/HDB2 P33/D3/HDB3 P34/D4/HDB4 P35/D5/HDB5 P36/D6/HDB6 P37/D7/HDB7 Port 2 Port 5 P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 Figure 1-1 Block Diagram 4 1.3 1.3.1 Pin Assignments and Functions Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3502 in the DP-64S packages. Figure 1-3 shows the pin arrangement in the FP-64A package. KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/P62/FTOB KEYIN3/P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2 RES XTAL EXTAL MD1 MD0 NMI VCC STBY VSS P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/P43/TMCI1 HIRQ1/P44/TMO1 HIRQ12/P45/TMRI1 CS2/P46/o GA20/P47 P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 KEYIN4/P70 KEYIN5/P71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 VCC P77/WAIT/HA0 P76/RD/IOR P75/WR/IOW P74/AS/CS1 P73/KEYIN7 P72/KEYIN6 Figure 1-2 Pin Arrangement (DP-64S, Top View) 5 P22/A10 P23/A11 P24/A12 35 P25/A13 34 48 47 46 45 44 43 42 41 40 39 38 37 36 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P30/D0/HDB0 P31/D1/HDB1 P32/D2/HDB2 P33/D3/HDB3 P34/D4/HDB4 P35/D5/HDB5 P36/D6/HDB6 P37/D7/HDB7 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 RES P26/A14 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 VSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 P27/A15 VCC HA0/P77/WAIT IOR/P76/RD IOW/P75/WR CS1/P74/AS KEYIN7/P73 KEYIN6/P72 KEYIN5/P71 KEYIN4/P70 P55/SCK1 P54/RxD1 P53/TxD1 P52/SCK0 P51/RxD0 P50/TxD0 HIRQ11/P43/TMCI1 HIRQ12/P45/TMRI1 HIRQ1/P44/TMO1 P40/TMCI0 P41/TMO0 P42/TMRI0 CS2/P46/o Figure 1-3 Pin Arrangement (FP-64A, Top View) 6 GA20/P47 MD1 XTAL EXTAL MD0 NMI VCC STBY VSS 1.3.2 Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 list the assignments of the pins of the DP-64S and FP-64A packages in each operating mode. Table 1-2 Pin Assignments in Each Operating Mode Expanded Modes Mode 1 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 RES XTAL EXTAL MD1 MD0 NMI VCC STBY VSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 o P47 P50/TxD0 P51/RxD0 P52/SCK0 Mode 2 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 RES XTAL EXTAL MD1 MD0 NMI VCC STBY VSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 o P47 P50/TxD0 P51/RxD0 P52/SCK0 Single-Chip Mode Mode 3 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 RES XTAL EXTAL MD1 MD0 NMI VCC STBY VSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ11 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ12 P46/o/CS2 P47/GA 20 P50/TxD0 P51/RxD0 P52/SCK0 7 Pin No. DP-64S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FP-64A 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Table 1-2 Pin Assignments in Each Operating Mode (cont) Expanded Modes Mode 1 P53/TxD1 P54/RxD1 P55/SCK1 P70/KEYIN4 P71/KEYIN5 P72/KEYIN6 P73/KEYIN7 AS WR RD P77/WAIT VCC A15 A14 A13 A12 A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 Mode 2 P53/TxD1 P54/RxD1 P55/SCK1 P70/KEYIN4 P71/KEYIN5 P72/KEYIN6 P73/KEYIN7 AS WR RD P77/WAIT VCC P27/A 15 P26/A 14 P25/A 13 P24/A 12 P23/A 11 P22/A 10 P21/A 9 P20/A 8 VSS P17/A 7 P16/A 6 P15/A 5 P14/A 4 P13/A 3 P12/A 2 P11/A 1 P10/A 0 Single-Chip Mode Mode 3 P53/TxD1 P54/RxD1 P55/SCK1 P70/KEYIN4 P71/KEYIN5 Pin No. DP-64S 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 FP-64A 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 P72/KEYIN6 P73/KEYIN7 P74/CS 1 P75/IOW P76/IOR P77/HA0 VCC P27 P26 P25 P24 P23 P22 P21 P20 VSS P17 P16 P15 P14 P13 P12 P11 P10 8 Table 1-2 Pin Assignments in Each Operating Mode (cont) Expanded Modes Mode 1 D0 D1 D2 D3 D4 D5 D6 D7 Mode 2 D0 D1 D2 D3 D4 D5 D6 D7 Single-Chip Mode Mode 3 P30/HDB0 P31/HDB1 P32/HDB2 P33/HDB3 P34/HDB4 P35/HDB5 P36/HDB6 P37/HDB7 Pin No. DP-64S 57 58 59 60 61 62 63 64 FP-64A 49 50 51 52 53 54 55 56 9 (2) Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3 Pin Functions Pin No. Type Power Symbol VCC DP-64S 14, 39 FP-64A 6, 31 I/O I Name and Function Power: Connected to the power supply. Connect both VCC pins to the system power supply. Ground: Connected to ground (0 V). Connect all V SS pins to the system power supply (0 V). Crystal: Connected to a crystal oscillator. The crystal frequency must be the same as the desired system clock frequency. If an external clock is input at the EXTAL pin, a reversephase clock should be input at the XTAL pin. External crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock must be the same as the desired system clock frequency. See section 6, Clock Pulse Generator, for examples of connections to a crystal and external clock. System clock: Supplies the system clock to peripheral devices. Reset: A low input causes the chip to reset. Standby: A transition to the hardware standby mode (a power-down state) occurs when a low input is received at the STBY pin. Address bus: Address output pins. VSS 16, 48 8, 40 I Clock XTAL 9 1 I EXTAL 10 2 I o System control RES STBY 23 8 15 15 64 7 O I I Address bus A15 to A 0 40 to 47, 49 to 56, 32 to 39, 41 to 48 O 10 Table 1-3 Pin Functions (cont) Pin No. Type Data bus Bus control Symbol D7 to D0 WAIT DP-64S 64 to 57 38 FP-64A 56 to 49 30 I/O I/O I Name and Function Data bus: 8-bit bidirectional data bus. Wait: Requests the CPU to insert T W states into the bus cycle when an offchip address is accessed. Read: Goes low to indicate that the CPU is reading an external address. Write: Goes low to indicate that the CPU is writing to an external address. Address strobe: Goes low to indicate that there is a valid address on the address bus. Non maskable interrupt: Highestpriority interrupt request. The NMIEG bit in the system control register determines whether the interrupt is requested on the rising or falling edge of the NMI input. Interrupt request 0 to 2: Maskable interrupt request pins. Mode: Input pins for setting the MCU operating mode according to the table below. MD1 0 MD0 1 Mode Mode 1 Description Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode RD WR AS 37 36 35 29 28 27 O O O Interrupt signals NMI 13 5 I IRQ0 to IRQ2 Operating mode control MD1, MD0 5 to 7 11 12 61 to 63 3 4 I I 1 0 Mode 2 1 1 Mode 3 11 Table 1-3 Pin Functions (cont) Pin No. Type 16-bit freerunning timer Symbol FTCI DP-64S 1 FP-64A 57 I/O I Name and Function FRT counter clock input: Input pin for an external clock signal for the freerunning counter. FRT output compare A: Output pins controlled by comparator A of the freerunning timer. FRT output compare B: Output pins controlled by comparator B of the freerunning timer. FRT input capture: Input capture pin for the free-running timer. 8-bit timer output (channels 0 and 1): Compare- match output pins for the 8-bit timers. 8-bit timer clock input (channels 0 and 1): External clock input pins for the 8-bit timer counters. 8-bit timer reset input (channels 0 and 1): High input at these pins resets the 8-bit timers. Serial transmit data (channels 0 and 1): Data output pins for the serial communication interface. Serial receive data (channels 0 and 1): Data input pins for the serial communication interface. Serial clock (channels 0 and 1): Input/output pins for the serial clock signals. FTOA 2 58 O FTOB 3 59 O FTI 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Serial communication interface (SCI) TxD0 TxD1 RxD0 RxD1 SCK 0 SCK 1 4 18 21 17 20 19 22 25 28 26 29 27 30 60 10 13 9 12 11 14 17 20 18 21 19 22 I O I I O I I/O 12 Table 1-3 Pin Functions (cont) Pin No. Type Generalpurpose I/O Symbol P17 to P10 DP-64S 49 to 56 FP-64A 41 to 48 I/O I/O Name and Function Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 2 data direction register (P2DDR). Port 3: An 8-bit input/output port with programmable MOS input pull-ups and LED drive capability. The direction of each bit can be selected in the port 3 data direction register (P3DDR). Port 4: An 8-bit input/output port. The direction of each bit (except P4 6) can be selected in the port 4 data direction register (P4DDR). Port 5: A 6-bit input/output port. The direction of each bit can be selected in the port 5 data direction register (P5DDR). Port 6: A 7-bit input/output port. The direction of each bit can be selected in the port 6 data direction register (P6DDR). Port 7: An 8-bit input/output port. The direction of each bit can be selected in the port 7 data direction register (P7DDR). P27 to P20 40 to 47 32 to 39 I/O P37 to P30 64 to 57 56 to 49 I/O P47 to P40 24 to 17 16 to 9 I/O P55 to P50 30 to 25 22 to 17 I/O P66 to P60 7 to 1 63 to 57 I/O P77 to P70 38 to 31 30 to 23 I/O 13 Table 1-3 Pin Functions (cont) Pin No. Type Host interface (HIF) Symbol HDB0 to HDB7 CS 1 CS 2 IOR IOW HA 0 DP-64S 57 to 64 FP-64A 49 to 56 I/O I/O Name and Function Host interface data bus: Bidirectional 8-bit bus for host interface access by the host. Chip select 1 and 2: Input pins for selecting host interface channel 1 or channel 2. I/O read: Input pin that enables reads on the host interface. I/O write: Input pin that enables writes to the host interface. Command/data: Input pin that indicates a data access or command access. GATE A20: GATE A 20 control signal output pin. Host interrupt 1, 11, 12: Output pins for interrupt requests to the host. Keyboard input: Input pins for a matrix keyboard. (P1 0 to P1 7 and P20 to P27 are normally used as keyboard scan outputs, enabling a maximum 16output x 8-input, 128-key matrix to be configured. The number of keys can be increased by using other port outputs.) 35 23 37 36 38 27 15 29 28 30 I I I I GA20 HIRQ1 HIRQ11 HIRQ12 Keyboard control KEYIN0 to KEYIN7 24 21 20 22 1 to 4 31 to 34 16 13 12 14 57 to 60 23 to 26 O O I 14 Section 2 CPU 2.1 Overview The H8/3502 has the generic H8/300 CPU: an 8-bit central processing unit with a speed-oriented architecture featuring sixteen general registers. This section describes the CPU features and functions, including a concise description of the addressing modes and instruction set. For further details on the instructions, see the H8/300 Series Programming Manual. 2.1.1 Features The main features of the H8/300 CPU are listed below. * Two-way register configuration -- Sixteen 8-bit general registers, or -- Eight 16-bit general registers * Instruction set with 57 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions * Eight addressing modes -- Register direct (Rn) -- Register indirect (@Rn) -- Register indirect with displacement (@(d:16, Rn)) -- Register indirect with post-increment or pre-decrement (@Rn+ or @-Rn) -- Absolute address (@aa:8 or @aa:16) -- Immediate (#xx:8 or #xx:16) -- PC-relative (@(d:8, PC)) -- Memory indirect (@@aa:8) * Maximum 64-kbyte address space * High-speed operation -- All frequently-used instructions are executed two to four states -- The maximum clock rate is 10 MHz/5 V (o clock) -- 8- or 16-bit register-register add or subtract: 200 ns (10 MHz) -- 8 x 8-bit multiply: 1400 ns (10 MHz) -- 16 / 8-bit divide: 1400 ns (10 MHz) * Power-down mode -- SLEEP instruction 15 2.1.2 Address Space The H8/300 CPU supports an address space of up to 64 kbytes for storing program code and data. The memory map is different for each mode (modes 1, 2, and 3). See section 3.5, Address Space Maps for Each Operating Mode, for details. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0 Control registers (CR) 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit CCR Figure 2-1 CPU Registers 16 2.2 2.2.1 Register Descriptions General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers. R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As indicated in figure 2-2, R7 (SP) points to the top of the stack. Unused area SP (R7) Stack area Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt mask bit (I). Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling. 17 Bit 6--User Bit (U): This bit can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5--Half-Carry (H): This bit is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4--User Bit (U): This bit can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative (N): This bit indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry (C): This bit is used by: * Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result * Shift and rotate instructions, to store the value shifted out of the most significant or least significant bit * Bit manipulation and bit load instructions, as a bit accumulator The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional branching instructions (Bcc). Some instructions leave some or all of the flag bits unchanged. The action of each instruction on the flag bits is shown in Appendix A.1, Instruction Set List. See the H8/300 Series Programming Manual for further details. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 18 2.3 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. * All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. * The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. 19 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 Don't care 7 0 1-bit data RnL Don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB Don't care 7 0 LSB Byte data RnL Don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH Don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL Don't care Legend RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 20 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB Note: * Ignored on returning Legend CCR: Condition code register Figure 2-4 Memory Data Formats The stack must always be accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are returned, the lower byte is ignored. 21 2.4 2.4.1 Addressing Modes Addressing Modes The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. (1) Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. (2) Register indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) Register Indirect with Displacement--@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with Post-Increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register Indirect with Pre-Decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit 22 immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) PC-Relative--@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. The result must be an even number. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). The word located at this address contains the branch address. Note that part of this area is located in the vector table. See section 3.5, Address Space Maps for Each Operating Mode, for details. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how an effective address (EA) is calculated in each addressing mode. Arithmetic and logic instructions (ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, XOR.B instructions) use (1) register direct and (6) immediate addressing modes. Data transfer instructions can use all addressing modes except (7) program-counter relative and (8) memory indirect. Bit manipulation instructions can use (1) register direct, (2) register indirect , or (5) absolute (@aa:8) addressing mode to specify an operand, and (1) register direct (BSET, BCLR, BNOT, and BTST instructions) or (6) immediate (3-bit) addressing mode to specify a bit number in the operand. 23 24 Effective Address Calculation 3 0 3 Table 2-2 Effective Address Calculation Effective Address (EA) 0 No. regm 87 43 0 Addressing Mode and Instruction Format (1) Register direct, (Rn) regn 15 op 15 0 regm regn Operand is regm/n contents reg contents (16 bits) 15 (2) 76 43 0 Register indirect (@Rn) 0 15 op 15 0 reg reg contents (16 bits) disp (3) 76 43 0 Register indirect with displacement (@d:16, Rn) op disp reg 15 0 15 (4) 15 0 15 0 Register indirect with post-increment or pre-decrement * Register indirect with post-increment, @Rn+ 76 43 0 reg contents (16 bits) 15 op 15 reg 1 or 2 0 * Register indirect with pre-decrement, @-Rn 76 43 0 reg contents (16 bits) 15 0 15 op reg 1 or 2 Incremented or decremented by 1 if operand is byte size, and by 2 if word size Table 2-2 Effective Address Calculation (cont) Effective Address Calculation 15 87 No. H'FF 0 Addressing Mode and Instruction Format Effective Address (EA) (5) 87 Absolute address @aa:8 op 15 0 0 15 abs 0 @aa:16 op abs 15 (6) 87 0 Immediate #xx:8 op 0 15 IMM Operand is 1- or 2-byte immediate data op IMM 15 0 #xx:16 15 (7) Program-counter relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp 25 26 Effective Address Calculation Effective Address (EA) 87 0 Table 2-2 Effective Address Calculation (cont) No. Addressing Mode and Instruction Format (8) Memory indirect, @@aa:8 15 op 15 87 0 abs H'00 15 0 Memory contents (16 bits) Legend reg, regm, regn: op: disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address 2.5 Instruction Set Table 2-1 lists the H8/300 CPU instruction set. Table 2-1 Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Notes: 1. 2. 3. Instruction Classification Instructions MOV, MOVTPE *1, MOVFPE*1, PUSH*2, POP*2 Types 3 14 4 8 14 5 8 1 Total 57 These instructions cannot be used with the H8/3502. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. Bcc is a conditional branch instruction in which cc represents a condition code. ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*3, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 27 Operation Notation Rd Rs Rn, Rm rn, rm 28 2.5.1 Data Transfer Instructions Table 2-2 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-2 Instruction MOV Data Transfer Instructions Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. Cannot be used with the H8/3502. Cannot be used with the H8/3502. Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. MOVTPE MOVFPE PUSH B B W POP W Note: * Size: operand size B: Byte W: Word 29 15 8 7 0 MOV Rm Rn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 Rn @Rm, or @Rm Rn op disp 15 8 7 rm rn @(d:16, Rm) Rn, or Rn @(d:16, Rm) 0 op 15 8 7 rm rn 0 @Rm+ Rn, or Rn @-Rm @aa:8 Rn, or Rn @aa:8 op 15 rn 8 7 abs 0 op abs 15 8 7 rn @aa:16 Rn, or Rn @aa:16 0 op 15 rn 8 7 #imm 0 #xx:8 Rn op #imm 15 8 7 rn #xx:16 Rn 0 op abs 15 8 7 rn MOVFPE, MOVTPE 0 op Legend op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address #imm: Immediate data rn PUSH, POP Figure 2-5 Data Transfer Instruction Codes 30 2.5.2 Arithmetic Operations Table 2-3 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations for their object codes. Table 2-3 Instruction ADD SUB Arithmetic Instructions Size* B/W Function Rd Rs Rd, Rd + #imm Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #imm C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. Rd #1 Rd Increments or decrements a general register. Rd #imm Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. Rd - Rs, Rd - #imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register. ADDX SUBX B INC DEC ADDS SUBS DAA DAS MULXU B W B B DIVXU B CMP B/W NEG B Note: * Size: operand size B: Byte W: Word 31 2.5.3 Logic Operations Table 2-4 describes the four instructions that perform logic operations. See figure 2-6 in section 2.5.4, Shift Operations for their object codes. Table 2-4 Instruction AND Logic Operation Instructions Size* B Function Rd Rs Rd, Rd #imm Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #imm Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) Rd Obtains the one's complement (logical complement) of general register contents. OR B XOR B NOT B Note: * Size: operand size B: Byte 2.5.4 Shift Operations Table 2-5 describes the eight shift instructions. Figure 2-6 shows the object code formats of the arithmetic, logic, and shift instructions. Table 2-5 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Shift Instructions Size* B B B B Function Rd shift Rd Performs an arithmetic shift operation on general register contents. Rd shift Rd Performs a logical shift operation on general register contents. Rd rotate Rd Rotates general register contents. Rd rotate through carry Rd Rotates general register contents through the C (carry) bit. Note: * Size: operand size B: Byte 32 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 #imm 0 ADD, ADDX, SUBX, CMP (#xx:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 #imm 0 AND, OR, XOR (#xx:8) op Legend Operation field op: rm, rn: Register field #imm: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 33 2.5.5 Bit Manipulations Table 2-6 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-6 Instruction BSET Bit-Manipulation Instructions Size* B Function 1 ( BCLR B BNOT B BTST B BAND BIAND B BOR BIOR B BXOR BIXOR B B 34 Table 2-6 Instruction BLD BILD Bit-Manipulation Instructions (cont) Size* B Function ( BST BIST B Note: * Size: operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are readmodify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers. Order Read Modify Write Operation Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address Example: BCLR is executed to clear bit 0 in the port 1 data direction register (P1DDR) under the following conditions. P1 7: Input pin, Low P1 6: Input pin, High P1 5-P1 0: Output pins, Low The intended purpose of this BCLR instruction is to switch P10 from output to input. 35 Before Execution of BCLR Instruction P17 Input/output Pin state DDR DR Input Low 0 1 P16 Input High 0 0 P15 Output Low 1 0 P14 Output Low 1 0 P13 Output Low 1 0 P12 Output Low 1 0 P11 Output Low 1 0 P10 Output Low 1 0 Execution of BCLR Instruction BCLR.B #0, @P1DDR ; Clear bit 0 in data direction register After Execution of BCLR Instruction P17 Input/output Pin state DDR DR Output Low 1 1 P16 P15 P14 Output Low 1 0 P13 Output Low 1 0 P12 Output Low 1 0 P11 Output Low 1 0 0 P10 Input High 0 Output Output High 1 0 Low 1 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P1DDR. Since P1DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P1DDR to complete the BCLR instruction. As a result, P10DDR is cleared to 0, making P10 an input pin. In addition, P17DDR and P16DDR are set to 1, making P1 7 and P16 output pins. 36 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 #imm rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn #imm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) 0 0 op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) Bit No.: register direct (Rm) 0 0 op op 15 8 7 abs #imm 0 0 0 0 0 Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) op op rm abs 0 0 0 0 Operand: absolute (@aa:8) Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 #imm rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn #imm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) 0 0 op op #imm abs 0 0 0 0 Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend Operation field op: rm, rn: Register field abs: Absolute address #imm: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 37 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 #imm rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn #imm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) 0 0 op op #imm abs 0 0 0 0 Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend Operation field op: rm, rn: Register field abs: Absolute address #imm: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont) 38 2.5.6 Branching Instructions Table 2-7 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-7 Instruction Bcc Branching Instructions Size -- Function Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE cc Field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP JSR BSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified displacement from the current address. Returns from a subroutine 39 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Legend op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2-8 Branching Instruction Codes 40 2.5.7 System Control Instructions Table 2-8 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-8 Instruction RTE SLEEP LDC System Control Instructions Size* -- -- B Function Returns from an exception-handling routine. Causes a transition to the power-down state. Rs CCR, #imm CCR Moves immediate data or general register contents to the condition code register. CCR Rd Copies the condition code register to a specified general register. CCR #imm CCR Logically ANDs the condition code register with immediate data. CCR #imm CCR Logically ORs the condition code register with immediate data. CCR #imm CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter. STC ANDC ORC XORC B B B B NOP -- Note: * Size: operand size B: Byte 41 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op #imm ANDC, ORC, XORC, LDC (#xx:8) Legend op: Operation field rn: Register field #imm: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-9 describes the EEPMOV instruction. Figure 2-10 shows its object code format. Table 2-9 Instruction EEPMOV Block Data Transfer Instruction Size -- Function if R4L 0 then repeat until else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. @R5+ @R6+ R4L - 1 R4L R4L = 0 42 15 8 7 0 op op Legend op: Operation field Figure 2-10 Block Data Transfer Instruction Notes on EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 H'FFFF Not allowed R6 + R4L R5 + R4L 43 2.6 2.6.1 CPU States Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. Figure 2-11 summarizes these states, and figure 2-12 shows a map of the state transitions. State Program execution state The CPU executes successive program instructions. Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Power-down state A state in which some or all of the chip functions are stopped to conserve power. Sleep mode Software standby mode Hardware standby mode Figure 2-11 Operating States 44 Interrupt request Exceptionhandling state Program execution state Exception handing Interrupt request SLEEP instruction with SSBY bit set SLEEP instruction Sleep mode RES = 1 NMI or IRQ0 to IRQ2 and IRQ6 Software standby mode Reset state STBY = 1, RES = 0 Hardware standby mode Power-down state Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode. 2. A transition from any state to the hardware standby mode occurs when STBY goes low. Figure 2-12 State Transitions 2.6.2 Program Execution State In this state the CPU executes program instructions in sequence. The main program, subroutines, and interrupt-handling routines are all executed in this state. 2.6.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and changes its normal processing flow. In interrupt exception handling, the CPU references the stack pointer (R7) and saves the program counter and condition code register on the stack. For further details see section 4, Exception Handling. 2.6.4 Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. 45 (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function. When an interrupt or reset signal is received, the CPU returns through the exception-handling state to the program execution state. (2) Software Standby Mode: The software standby mode is entered if the SLEEP instruction is executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, but the contents of the on-chip RAM and CPU registers remain unchanged. I/O port outputs also remain unchanged. (3) Hardware Standby Mode: The hardware standby mode is entered when the input at the STBY pin goes low. All chip functions halt, including I/O port output. The on-chip supporting modules are initialized, but on-chip RAM contents are held. See section 18, Power-Down State, for further information. 2.7 Access Timing and Bus Cycle The CPU is driven by the system clock (o). The period from one rising edge of the system clock to the next is referred to as a "state." Memory access is performed in a two- or three-state bus cycle as described below. Different accesses are performed to on-chip memory, the on-chip register field, and external devices. For more detailed timing diagrams of the bus cycles, see section 19, Electrical Specifications. 2.7.1 Access to On-Chip Memory (RAM and ROM) On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or word data can be accessed, via a 16-bit data bus. Figure 2-13 shows the on-chip memory access cycle. Figure 2-14 shows the associated pin states. 46 Bus cycle T1 state o T2 state Internal address bus Address Internal read signal Internal data bus (read) Read data Internal write signal Internal data bus (write) Write data Figure 2-13 On-Chip Memory Access Cycle 47 Bus cycle T1 state o T2 state Address bus Address AS: High RD: High WR: High Data bus: High impedance state Figure 2-14 Pin States during On-Chip Memory Access Cycle 48 2.7.2 Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2-15 shows the access cycle for the on-chip register field. Figure 2-16 shows the associated pin states. Figures 2-17 (a) and (b) show the read and write access timing for external devices. Bus cycle T1 state o Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) T2 state T3 state Address Read data Write data Figure 2-15 On-Chip Register Field Access Cycle 49 Bus cycle T1 state o T2 state T3 state Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2-16 Pin States during On-Chip Supporting Module Access 50 Read cycle T1 state o T2 state T3 state Address bus Address AS RD WR: High Data bus Read data Figure 2-17 (a) External Device Access Timing (Read) 51 Write cycle T1 state o T2 state T3 state Address bus Address AS RD: High WR Data bus Write data Figure 2-17 (b) External Device Access Timing (Write) 52 Section 3 MCU Operating Modes and Address Space 3.1 3.1.1 Overview Operating Modes The H8/3502 operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD 0). See table 3-1. Table 3-1 Mode Mode 0 Mode 1 Mode 2 Mode 3 Operating Modes MD1 Low Low High High MD0 Low High Low High Address Space -- Expanded Expanded Single-chip On-Chip ROM -- Disabled Enabled Enabled On-Chip RAM -- Enabled* Enabled* Enabled Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can be accessed instead. Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. The maximum address space supported by these externally expanded modes is 64 kbytes. In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used. All ports are available for general-purpose input and output. Mode 0 is inoperative in the H8/3502. Avoid setting the mode pins to mode 0. 3.1.2 Mode and System Control Registers Table 3-2 lists the registers related to the chip's operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD0. Table 3-2 Name System control register Mode control register Mode and System Control Registers Abbreviation SYSCR MDCR Read/Write R/W R Address H'FFC4 H'FFC5 53 3.2 Bit System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write The system control register (SYSCR) is an 8-bit register that controls the operation of the chip. Bit 7--Software Standby (SSBY): Enables transition to the software standby mode. For details, see section 18, Power-Down State. On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It can be cleared by writing 0. Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to sleep mode. The SLEEP instruction causes a transition to software standby mode. (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 8 ms. For specific settings, see section 18.3.3, Clock Settling Time for Exit from Software Standby Mode. Bit 6 STS2 0 0 0 0 1 1 Bit 5 STS1 0 0 1 1 0 1 Bit 4 STS0 0 1 0 1 -- -- Description Settling time = 8,192 states Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Unused (Initial value) 54 Bit 3--External Reset (XRST): Indicates the source of a reset. A reset can be generated by input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3 XRST 0 1 Description Reset was caused by watchdog timer overflow. Reset was caused by external input. (Initial value) Bit 2--NMI Edge (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG 0 1 Description An interrupt is requested on the falling edge of the NMI input. An interrupt is requested on the rising edge of the NMI input. (Initial value) Bit 1--Host Interface Enable (HIE): Enables or disables the host interface function. When enabled, the host interface processes host-slave data transfers, operating in slave mode. Bit 1 HIE 0 1 Description The host interface is disabled. The host interface is enabled (slave mode). (Initial value) Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0 RAME 0 1 Description The on-chip RAM is disabled. The on-chip RAM is enabled. (Initial value) 55 3.3 Bit Mode Control Register (MDCR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 -- 3 -- 0 -- 2 -- 1 -- 1 MDS1 * R 0 MDS0 * R Initial value Read/Write Note: * Initialized according to MD1 and MD0 inputs. The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 0. Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1 corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode control register is read, the levels at the mode pins (MD1 and MD 0) are latched in these bits. 3.4 Mode Descriptions Mode 1 (Expanded Mode without On-Chip ROM): Mode 1 supports a 64-kbyte address space most of which is off-chip. In particular, the interrupt vector table is located in off-chip memory. The on-chip ROM is not used. Software can select whether to use the on-chip RAM. Ports 1, 2, 3 and 7 are used for the address and data bus lines and control signals as follows: Ports 1 and 2: Address bus Port 3: Data bus Port 7 (partly): Bus control signals Mode 2 (Expanded Mode with On-Chip ROM): Mode 2 supports a 64-kbyte address space which includes the on-chip ROM. Software can select whether or not to use the on-chip RAM, and can select the usage of pins in ports 1 and 2. Ports 1 and 2: Address bus (see note) Port 3: Data bus Port 7 (partly): Bus control signals 56 Note: In mode 2, ports 1 and 2 are initially general-purpose input ports. Software must change the desired pins to output before using them for the address bus. See section 7, I/O Ports for details. Mode 3 (Single-Chip Mode): In this mode all memory is on-chip. Since no off-chip memory is accessed, there is no external address bus. All ports are available for general-purpose input and output. 3.5 Address Space Maps for Each Operating Mode Figure 3-1 shows memory maps of the H8/3502 in each of the three operating modes. 57 Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0063 H'0064 H'0063 H'0064 H'0000 Mode 2 Expanded mode with on-chip ROM H'0000 Vector table H'0063 H'0064 Mode 3 Single-chip mode Vector table On-chip ROM, 16384 bytes On-chip ROM, 16384 bytes External address space H'3FFF H'4000 Reserved*2 H'7FFF H'8000 External address space H'FB7F H'FB80 Reserved*1, *2 H'FD7F H'FD80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FD7F H'FD80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FB7F H'FB80 Reserved*1, *2 H'FD7F H'FD80 On-chip RAM, 512 bytes H'FF7F External address space H'FF90 On-chip I/O register field H'FFFF On-chip I/O register field H'FB80 Reserved*2 H'7FFF H'3FFF Reserved*2 On-chip RAM*1, 512 bytes External address space On-chip I/O register field On-chip RAM*1, 512 bytes Notes: *1. External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. *2. Do not access reserved areas. Figure 3-1 Address Space Map 58 Section 4 Exception Handling 4.1 Overview The H8/3502 recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4-1 Priority High Reset and Interrupt Exceptions Type of Exception Reset Detection Timing Clock synchronous Timing of Exception-Handling Sequence When RES goes low, the chip enters the reset state immediately. The hardware exceptionhandling sequence (reset sequence) begins as soon as RES goes high again. When an interrupt is requested, the hardware exception-handling sequence (interrupt sequence) begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence. Interrupt On completion of instruction execution* Low Note: * Not detected in case of ANDC, ORC, XORC, and LDC instructions. 4.2 4.2.1 Reset Overview A reset has the highest exception-handling priority. When the RES pin goes low or a watchdog reset is started (watchdog timer overflow for which the reset option is selected), all current processing stops and the chip enters the reset state. The internal state of the CPU and the registers of the on-chip supporting modules are initialized. When RES returns from low to high or the watchdog reset pulse ends, the chip comes out of the reset state via the reset exception-handling sequence. 59 4.2.2 Reset Sequence The reset state begins when RES goes low or a watchdog reset occurs. To ensure correct resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during operation, the RES pin should be held low for at least 10 system clock (o) cycles. The watchdog reset pulse width is always 518 system clock cycles. For details of pin states in a reset, see appendix D, Pin States. When reset exception handling is started, hardware carries out the following reset sequence. 1. 2. 3. In the condition code register (CCR), the I bit is set to 1 to mask interrupts. The registers of the I/O ports and on-chip supporting modules are initialized. The CPU loads the program counter with the first word in the vector table (stored at addresses H'0000 and H'0001) and starts program execution. The RES pin should be held low when power is switched off, as well as when power is switched on. Figure 4-1 indicates the timing of the reset sequence when the vector table and reset routine are located in on-chip ROM (mode 2 or 3). Figure 4-2 indicates the timing when they are in off-chip memory (mode 1). 60 Vector fetch RES/watchdog reset (internal) o Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (2) Internal Instruction processing prefetch (1) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 4-1 Reset Sequence (Mode 2 or 3, Program Area in On-Chip ROM) 61 62 Vector fetch Internal processing Instruction prefetch (1) (3) (5) (7) (2) (4) (6) (8) Reset exception handling vector address: (1) = H'0000, (3) = H'0001 Start address (contents of reset exception handling vector address): (2) = upper byte, (4) = lower byte Start address: (5) = (2) (4), (7) = (2) (4) + 1 First instruction of program: (6) = first byte, (8) = second byte RES/watchdog reset (internal) o A15 to A0 RD Figure 4-2 Reset Sequence (Mode 1) WR D7 to D0 (8 bits) (1), (3) (2), (4) (5), (7) (6), (8) 4.2.3 Disabling of Interrupts after Reset All interrupts, including NMI, are disabled immediately after a reset. The first program instruction, located at the address specified at the top of the vector table, is therefore always executed. To prevent program crashes, this instruction should initialize the stack pointer (example: MOV.W #xx:16, SP). After execution of this instruction, the NMI interrupt is enabled. Other interrupts remain disabled until their enable bits are set to 1. After reset exception handling, a CCR manipulation instruction can be executed to fix the CCR contents before the instruction that initializes the stack pointer. After the CCR manipulation instruction is executed, all interrupts, including NMI, are disabled. The next instruction should be the instruction that initializes the stack pointer. 4.3 4.3.1 Interrupts Overview There are twelve input pins for five external interrupt sources (NMI, IRQ0 to IRQ2, and IRQ6). There are also 21 internal interrupts originating on-chip. The features of these interrupts are: * All internal and external interrupts except NMI can be masked by the I bit in the CCR. * IRQ0 to IRQ2 and IRQ 6 can be falling-edge-sensed or level-sensed. The type of sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the rising or falling edge can be selected. * Interrupts are individually vectored. The software interrupt-handling routine does not have to determine what type of interrupt has occurred. * IRQ6 is requested by eight external sources (KEYIN0 to KEYIN7). KEYIN0 to KEYIN7 can be masked individually by the user program. * The watchdog timer can be made to generate an NMI interrupt or OVF interrupt according to its use. For details, see section 12, Watchdog Timer. Table 4-2 lists all the interrupts in their order of priority and gives their vector numbers and the addresses of their entries in the vector table. 63 Table 4-2 Interrupts No. 3 4 5 6 7 to 9 (KEYIN0 to KEYIN 7) 10 Address of Entry in Vector Table Priority H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'0013 H'0014 to H'0015 High Interrupt Source NMI IRQ0 IRQ1 IRQ2 Reserved IRQ6 Reserved Host interface IBF1 (IDR1 reception complete) IBF2 (IDR2 reception complete) 16-bit free-running timer 8-bit timer 0 ICI OCIA OCIB FOVI (Input capture) (Output compare A) (Output compare B) (Overflow) 11 to 16 H'0016 to H'0021 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 H'0046 to H'0047 H'0048 to H'0049 CMI0A (Compare-match A) CMI0B (Compare-match B) OVI0 (Overflow) CMI1A (Compare-match A) CMI1B (Compare-match B) OVI1 (Overflow) ERI0 RXI0 TXI0 TEI0 ERI1 RXI1 TXI1 TEI1 (Receive error) (Receive end) (TDR empty) (TSR empty) (Receive error) (Receive end) (TDR empty) (TSR empty) 8-bit timer 1 Serial communication interface 0 Serial communication interface 1 Reserved Watchdog timer Reserved Notes: 1. 2. 37 to 43 H'004A to H'0057 WOVF (WDT overflow) 44 H0058 to H'0059 Low 45 to 49 H'005A to H'0063 H'0000 and H'0001 contain the reset vector. H'0002 to H'0005 are reserved in the H8/3502 and are not available to the user. 64 4.3.2 Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask register (KMIMR). Table 4-3 Name System control register IRQ sense control register IRQ enable register Keyboard matrix interrupt mask register Registers Read by Interrupt Controller Abbreviation SYSCR ISCR IER KMIMR Read/Write R/W R/W R/W R/W Address H'FFC4 H'FFC6 H'FFC7 H'FFF1 (1) System Control Register (SYSCR)--H'FFC4 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Bit 2--Nonmaskable Interrupt Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the falling or rising edge of the NMI input signal. Bit 2 NMIEG 0 1 Description An interrupt is generated on the falling edge of NMI An interrupt is generated on the rising edge of NMI (Initial value) See section 3.2, System Control Register (SYSCR), for information on the other SYSCR bits. 65 (2) IRQ Sense Control Register (ISCR)--H'FFC6 Bit Initial value Read/Write 7 -- 1 -- 6 IRQ6SC 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 0 R/W 1 0 R/W 0 0 R/W IRQ2SC IRQ1SC IRQ0SC Bits 0 to 2 and 6--IRQ0 to IRQ2, IRQ6 Sense Control (IRQ0SC to IRQ2SC, IRQ6SC): These bits select how the input at pins IRQ0 to IRQ2 and KEYIN0 to KEYIN7 is sensed. Bit i (i = 0 to 2, 6) IRQiSC 0 1 Description The low level of IRQ0 to IRQ2 or KEYIN0 to KEYIN7 generates an interrupt request The falling edge of IRQ0 to IRQ2 or KEYIN0 to KEYIN7 generates an interrupt request (Initial value) (3) IRQ Enable Register (IER)--H'FFC7 Bit Initial value Read/Write 7 -- 1 -- 6 IRQ6E 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Bits 0 to 2, 6--IRQ0 to IRQ2 and IRQ6 Enable (IRQ0E to IRQ2E, IRQ6E): These bits enable or disable the IRQ 0, IRQ1, IRQ2, and IRQ6 interrupts individually. Bit i (i = 0 to 2, 6) IRQiE 0 1 Description IRQ0 to IRQ 2 and IRQ6 are disabled IRQ0 to IRQ 2 and IRQ6 are enabled (Initial value) When edge sensing is selected (by setting bits IRQ0SC to IRQ2SC and IRQ6SC to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (IRQ0E to IRQ2E and IRQ6E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit (IRQ0E to IRQ2E and IRQ6E) is set to 1, the request will be held pending until served. If the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the interrupt-handling routine can be executed even though the enable bit is now 0. 66 If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. 2. 3. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically when execution jumps to an interrupt vector. Clear the desired bits from IRQ0E, IRQ1E, IRQ2E, and IRQ6E to 0 to disable new interrupt requests. Clear the corresponding bits from IRQ0SC, IRQ1SC, IRQ2SC, and IRQ6SC to 0, then set them to 1 again. Pending IRQn interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0. (4) Keyboard Matrix Interrupt Mask Register (KMIMR) KMIMR is an 8-bit readable/writable register used in keyboard matrix scanning and sensing. To enable key-sense input interrupts from two or more pins during keyboard scanning and sensing, clear the corresponding mask bits to 0. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Bits 7 to 0--Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control key-sense input interrupt requests KEYIN7 to KEYIN0. Bits 7 to 0 KMIMR7 to KMIMR0 0 1 Description Key-sense input interrupt request is enabled. Key-sense input interrupt request is disabled. (Initial value) Figure 4-3 shows the relationship between the IRQ6 interrupt and KMIMR. 67 KMIMR0 (1) P60/KEYIN0 IRQ6 internal signal KMIMR1 (1) P61/KEYIN1 . . . . . . . . . . . . . . . Edge/level select and enable/ disable control IRQ6E IRQ6 interrupt KMIMR6 (1) P72/KEYIN6 IRQ6SC . . . . KMIMR7 (1) P73/KEYIN7 . . . . Initial values are given in parentheses Figure 4-3 KMIMR and IRQ6 Interrupt 4.3.3 External Interrupts There are five external interrupts: NMI, IRQ 0 to IRQ2, and IRQ6. These can be used to return from software standby mode. (1) NMI: NMI is the highest-priority interrupt, and is always accepted regardless of the value of the I bit in CCR. Interrupts from the NMI pin are edge-sensed: rising edge or falling edge can be specified by the NMIEG bit in SYSCR. The NMI exception handling vector number is 3. NMI exception handling sets the I bit in CCR to 1. (2) IRQ0 to IRQ2 and IRQ6: Interrupts IRQ0 to IRQ2 are requested by input signals on pins IRQ0 to IRQ2. The IRQ6 interrupt is requested by input signals on pins KEYIN0 to KEYIN7. Interrupts IRQ 0 to IRQ2 and IRQ 6 can be specified as falling-edge-sensed or level-sensed by bits IRQ0SC to IRQ2SC and IRQ6SC in ISCR. Interrupt requests are enabled by set bits IRQ0E to IRQ2E and IRQ6E to 1 in IER. Interrupts are masked by setting the I bit to 1 in CCR. 68 The IRQ6 input signal is generated as the logical OR of the key-sense inputs. When pins KEYIN0 to KEYIN7 (P60 to P63 and P70 to P73) are used as key-sense inputs, the corresponding KMIMR bits should be cleared to 0 to enable the corresponding key-sense interrupts. KMIMR bits corresponding to unused key-sense inputs should be set to 1 to disable those interrupts. All eight key-sense input interrupts are combined into a single IRQ6 interrupt. When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ2 and IRQ 6 have interrupt vector numbers 4 to 6 and 10. They are prioritized in order from IRQ6 (low) to IRQ0 (high). For details, see table 4-2. Interrupts IRQ 0 to IRQ2 and IRQ 6 do not depend on whether pins IRQ0 to IRQ2 and KEYIN0 to KEYIN7 are used as input pins or output pins. When interrupts IRQ 0 to IRQ2 and IRQ 6 are requested by an external signal, clear the corresponding DDR bits to 0 and use the pins as input/output pins. 4.3.4 Internal Interrupts Twenty-one internal interrupts can be requested by the on-chip supporting modules. All of them are masked when the I bit in the CCR is set. In addition, they can all be enabled or disabled by bits in the control registers of the on-chip supporting modules. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except NMI). The vector numbers of these interrupts are 17 to 36 and 44. For the priority order of these interrupts, see table 4-2. 4.3.5 Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4-4 shows a block diagram of the interrupt controller. 69 NMI interrupt IRQ0 flag IRQ0E * IRQ0 interrupt Priority decision Interrupt controller CPU Interrupt request Vector number OVF OVIE WOVF interrupt I (CCR) Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ0 edge IRQ0E IRQ0 flag S Q IRQ0 interrupt Figure 4-4 Block Diagram of Interrupt Controller The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU's interrupt mask bit (I) to 1. Accordingly, these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0. The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware standby mode. When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) When notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the CPU starts the hardware exception-handling sequence for the interrupt and latches the vector number. 70 Figure 4-5 is a flowchart of the interrupt (and reset) operations. Figure 4-7 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM and the stack is in on-chip RAM. (1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. (2) The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests remain pending. (3) Among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the CPU. Other interrupt requests remain pending. (4) When it receives the interrupt request, the CPU waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exceptionhandling sequence for the interrupt and latches the interrupt vector number. (5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the stack. See figure 4-6. The stacked PC indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. (6) Next the I bit in CCR is set to 1, masking all further interrupts except NMI. (7) The vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. 71 Program execution Interrupt requested? Yes Yes NMI? No No No I = 0? Yes IRQ0? Yes IRQ1? Yes WOVF? Yes No No Pending Latch vector No. Save PC Reset Save CCR I1 Read vector address Branch to software interrupt-handling routine Figure 4-5 Hardware Interrupt-Handling Sequence 72 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP(R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PC (upper byte) PC (lower byte) Even address Before interrupt is accepted Pushed onto stack After interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved and restored by word access at an even address. * Ignored on return. Figure 4-6 Usage of Stack in Interrupt Handling Although the CCR consists of only one byte, it is treated as word data when pushed on the stack. In the hardware interrupt exception-handling sequence, two identical CCR bytes are pushed onto the stack to make a complete word. When popped from the stack by an RTE instruction, the CCR is loaded from the byte stored at the even address. The byte stored at the odd address is ignored. 73 Interrupt accepted Interrupt priority decision. Wait for Instruction Internal end of instruction prefetch processing Interrupt request signal Vector table fetch Stack Instruction prefetch (first instruction of Internal interrupt-handling process- routine) ing o Internal address bus (1) (3) (5) (6) (8) (9) Internal read signal Internal write signal Internal 16-bit data bus (2) (4) (1) (7) (9) (10) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (6) SP-4 (7) CCR (8) Vector address (9) Start address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine (1) Figure 4-7 Timing of Interrupt Sequence 74 4.3.6 Interrupt Response Time Table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since the H8/3502 accesses its on-chip memory 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM. Table 4-4 Number of States before Interrupt Service Number of States No. 1 2 3 4 5 6 Reason for wait Interrupt priority decision Wait for completion of current instruction*1 Save PC and CCR Fetch vector Fetch instruction Internal processing Total Notes: 1. 2. 3. On-Chip Memory 2*3 1 to 13 4 2 4 4 17 to 29 External Memory 2*3 5 to 17 *2 12*2 6*2 12*2 4 41 to 53 *2 These values do not apply if the current instruction is an EEPMOV instruction. If wait states are inserted in external memory access, these values may be longer. 1 for internal interrupts. 4.3.7 Precaution Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. Similar considerations apply when an interrupt request flag is cleared to 0. Figure 4-8 shows an example in which the OCIAE bit is cleared to 0. 75 CPU write cycle to TIER o Internal address bus TIER address OCIA interrupt handling Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4-8 Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (I) is set to 1. 4.4 Note on Stack Handling In word access, the least significant bit of the address is always assumed to be 0. The stack is always accessed by word access. Care should be taken to keep an even value in the stack pointer (general register R7). Use the PUSH and POP (or MOV.W Rn, @-SP and MOV.W @SP+, Rn) instructions to push and pop registers on the stack. Setting the stack pointer to an odd value can cause programs to crash. Figure 4-9 shows an example of damage caused when the stack pointer contains an odd address. 76 PCH SP PCL SP R1L PCL H'FEFC H'FEFD SP H'FEFF BSR instruction MOV.B R1L, @-R7 H'FEFF set in SP Stack accessed beyond SP PCH is lost PCH: PCL: R1L: SP: Upper byte of program counter Lower byte of program counter General register R1L Stack pointer Figure 4-9 Example of Damage Caused by Setting an Odd Address in R7 4.5 Notes on the Use of Key-Sense Interrupts The H8/3502 incorporates a key-sense interrupt function which can be used in any operating mode. When used in a mode other than slave mode (when the host interface is disabled), the following points must be noted. In order to use the key-sense interrupt function, it is necessary to write to KMIMR to unmask the relevant KEYIN pins. If MOS pull-up transistors are provided on pins P73 to P70 and P63 to P60, KMPCR must also be written to. KMIMR and KMPCR can only be accessed when the HIE bit in SYSCR is set to 1. Consequently, the chip is in slave mode during this period. In slave mode, pin states may vary. (1) When KMIMR and KMPCR are set in the initialization routine directly after a reset External circuitry must be used such that no problem will be caused irrespective of whether the host interface output and I/O pins retain the high-impedance state or are set to the output 77 state. There are four host interface output pins--GA20, HIRQ12, HIRQ1, and HIRQ11--all of which are set to the port function (input state) initially. There are eight host interface I/O pins, HDB7 to HDB0; in single-chip mode, these are outputs when the P76/IOR pin is low and either one, or both, of the P75/CS1 and P45/CS2 pins is low. In expanded mode, these pins function as data bus pins (D7 to D0), and therefore the pin states do not vary. (2) When KMIMR and KMPCR are set other than in the initialization routine The states of the host interface input and I/O pins, and the pins with which they are multiplexed, may vary as a result of setting the HIE bit. P77/HA0, P76/IOR, P75/IOW, P7 5/CS1, P46/CS2, and P37/HDB7 to P30/HDB0 automatically become input pins and I/O pins. When a particular pin is used, it is designated as a port input pin or expanded bus control pin, and in single-chip mode, it is necessary to prevent the occurrence of a low level of the P76/IOR pin together with a low level of the P75/CS1 pin or the P46/CS2 pin, or both. In expanded mode, if external space is accessed when the HIE bit is set to 1, both the P7 6/IOR/RD pin and the P75/CS1/AS pin are driven low automatically. Note that the output values of P44/HIRQ12, P43/HIRQ1, and P42/HIRQ11 may vary as a result. 78 Section 5 Wait-State Controller 5.1 Overview The H8/3502 has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. * Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode * Automatic insertion of zero to three wait states 5.1.2 Block Diagram Figure 5-1 shows a block diagram of the wait-state controller. Internal data bus Wait request signal WAIT Wait-state controller (WSC) WSCR Legend WSCR: Wait-state control register Figure 5-1 Block Diagram of Wait-State Controller 79 5.1.3 Input/Output Pins Table 5-1 summarizes the wait-state controller's input pin. Table 5-1 Name Wait Wait-State Controller Pins Abbreviation WAIT I/O Input Function Wait request signal for access to external addresses 5.1.4 Register Configuration Table 5-2 summarizes the wait-state controller's register. Table 5-2 Name Wait-state control register Register Configuration Abbreviation WSCR R/W R/W Initial Value H'C8 Address H'FFC2 5.2 5.2.1 Register Description Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. It also controls frequency division of the clock signals supplied to the supporting modules. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 0 R/W 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W WSCR is initialized to H'C8 by a reset and in hardware standby mode. It is not initialized in software standby mode. 80 Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1 and WMS0): These bits select the wait mode. Bit 3 WMS1 0 Bit 2 WMS0 0 1 1 0 1 Description Programmable wait mode No wait states inserted by wait-state controller Pin wait mode Pin auto-wait mode (Initial value) Bits 1 and 0--Wait Count 1 and 0 (WC1 and WC0): These bits select the number of wait states inserted in access to external address areas. Bit 1 WC1 0 Bit 0 WC0 0 1 1 0 1 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 81 5.3 Wait Modes Programmable Wait Mode: The number of wait states (TW ) selected by bits WC1 and WC0 are inserted in all accesses to external addresses. Figure 5-2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). T1 T2 TW T3 o Address bus External address AS RD Read access Data bus Read data WR Write access Data bus Write data Figure 5-2 Programmable Wait Mode 82 Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (o) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. Figure 5-3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. Inserted by wait count T1 o T2 TW Inserted by WAIT pin TW T3 * * WAIT pin Address bus External address AS Read access RD Read data Data bus WR Write access Data bus Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5-3 Pin Wait Mode 83 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (o) in the T2 state, the number of wait states (TW ) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 5-4 shows the timing when the wait count is 1. T1 T2 T3 T1 T2 TW T3 o * * WAIT pin Address bus External address External address AS RD Read access Data bus Read data Read data WR Write access Data bus Write data Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5-4 Pin Auto-Wait Mode 84 Section 6 Clock Pulse Generator 6.1 Overview The H8/3502 has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a prescaler that generates clock signals for the on-chip supporting modules. 6.1.1 Block Diagram Figure 6-1 shows a block diagram of the clock pulse generator. XTAL EXTAL Oscillator circuit Duty adjustment circuit o (system clock) oP (for supporting modules) Prescaler Frequency divider (1/2) CKDBL oP/2 to oP/4096 Figure 6-1 Block Diagram of Clock Pulse Generator Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and EXTAL pins. The system clock frequency (o) will be the same as the input frequency. This same system clock frequency (oP) can be supplied to timers and other supporting modules, or it can be divided by two. The selection is made by software, by controlling the CKDBL bit. 85 6.1.2 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait-state insertion. WSCR is initialized to H'C8 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 0 R/W 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bit 5--Clock Double (CKDBL): Controls the frequency division of clock signals supplied to supporting modules. CKDBL Bit 5 0 1 Description The undivided system clock (o) is supplied as the clock (o P ) for supporting modules (Initial value) The system clock (o) is divided by two and supplied as the clock (o P ) for supporting modules Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1 and WMS0) Bits 1 and 0--Wait Count 1 and 0 (WC1 and WC0) These bits control wait-state insertion. For details, see section 5, Wait-State Controller. 86 6.2 Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. (1) Connecting an External Crystal Circuit Configuration: An external crystal can be connected as shown in the example in figure 62. Table 6-1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal should be used. C L1 EXTAL XTAL Rd C L2 C L1 = C L2 = 10 pF to 22 pF Figure 6-2 Connection of Crystal Oscillator (Example) Table 6-1 Damping Resistance 4 500 8 200 10 0 Frequency (MHz) Rd max () 87 Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6-2. CL L XTAL Rs EXTAL C0 AT-cut parallel resonating crystal Figure 6-3 Equivalent Circuit of External Crystal Table 6-2 External Crystal Parameters 4 120 8 80 7 pF max 10 70 Frequency (MHz) Rs max () C0 (pF) Use a crystal with the same frequency as the desired system clock frequency (o). 88 Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6-4. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Not allowed Signal A Signal B C L2 XTAL EXTAL C L1 Figure 6-4 Notes on Board Design around External Crystal 89 (2) Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high during standby. If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF. EXTAL External clock input XTAL Open (a) Connections with XTAL pin left open EXTAL 74HC04 XTAL External clock input (b) Connections with inverted clock input at XTAL pin Figure 6-5 External Clock Input (Example) 90 External Clock Input: The external clock signal should have the same frequency as the desired system clock (o). Clock timing parameters are given in table 6-3 and figure 6-6. Table 6-3 Clock Timing VCC = 5.0 V 10% Item Low pulse width of external clock input High pulse width of external clock input External clock rise time External clock fall time Clock pulse width low Symbol t EXL t EXH t EXr t EXf t CL t CH Min 40 40 -- -- 0.3 0.4 Clock pulse width high 0.3 0.4 Max -- -- 10 10 0.7 0.6 0.7 0.6 Unit ns ns ns ns t cyc t cyc t cyc t cyc o 5 MHz o < 5 MHz o 5 MHz o < 5 MHz Figure 16-4 Test Conditions Figure 6-6 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 6-6 External Clock Input Timing 91 Table 6-4 shows the external clock output settling delay time, and figure 6-7 shows the external clock output settling delay timing. The oscillator circuit and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the EXTAL pin. When the specified clock signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state during this time. Table 6-4 External Clock Output Settling Delay Time (Conditions: VCC = 4.5 V to 5.5 V, VSS = 0 V) Item External clock output settling delay time Symbol t DEXT * Min 500 Max -- Unit s Notes Figure 6-7 Note: * t DEXT includes an RES pulse width (t RESW) of 10 t cyc . VCC 4.5 V STBY VIH EXTAL o (internal or external) RES tDEXT* Note: * tDEXT includes an RES pulse width (tRESW) of 10 tcyc . Figure 6-7 External Clock Output Settling Delay Time Timing 92 6.3 Duty Adjustment Circuit When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock (o). 6.4 Prescaler The 1/2 frequency divider generates an on-chip supporting module clock (oP) from the system clock (o) according to the setting of the CKDBL bit. The prescaler divides the frequency of oP to generate internal clock signals with frequencies from o P/2 to oP/4096. 93 94 Section 7 I/O Ports 7.1 Overview The H8/3502 has five 8-bit input/output ports, one 7-bit input/output port, and one 6-bit input/output port. Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port pins are multiplexed, and the pin functions differ depending on the operating mode. Each port has a data direction register (DDR) that selects input or output, and a data register (DR) that stores output data. If bit manipulation instructions will be executed on the port data direction registers, see "Notes on Bit Manipulation Instructions" in section 2.5.5, Bit Manipulations. Ports 1, 2, 3, 6, and 7 can drive one TTL load and a 90-pF capacitive load. Port 4 (excluding pin P4 6) and port 5 can drive one TTL load and a 30-pF capacitive load. Ports 1, 2, and 3 can drive LEDs (with 10-mA current sink). Ports 1 to 7 can drive a Darlington transistor. Ports 1 to 3 and pins P60 to P63 and P70 to P73 have built-in MOS pull-ups. For block diagrams of the ports, see appendix C, I/O Port Block Diagrams. 95 Table 7-1 Port Functions Expanded Modes Single-Chip Mode Mode 3 General input/ output Port Port 1 Description * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups * 8-bit I/O port Pins P17 to P1 0/ A7 to A 0 Mode 1 Lower address output (A 7 to A0 ) Mode 2 Lower address output (A 7 to A 0) or general input Port 2 P27 to P2 0/ A15 to A 8 Upper address output (A 15 to A8) Upper address output (A 15 to A8) or general input General input/ output Port 3 Data bus (D7 to D0) P37 to P3 0/ D7 to D0/ HDB7 to HDB 0 Host interface data bus (HDB7 to HDB0) or general input/ output Port 4 P47/GA 20 P46/o/CS2 Host interface control output (GA20) or general input/ output o output Host interface control input (CS 2), general input, or o output P45/TMRI1/ HIRQ12 P44/TMO1/ HIRQ1 P43/TMCI1/ HIRQ11 P42/TMRI0 P41/TMO0 P40/TMCI0 Host interface host CPU interrupt request output (HIRQ12, HIRQ1, HIRQ11), 8-bit timer 0 and 1 input/ output (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1), and general input/output 96 Table 7-1 Port Functions (cont) Expanded Modes Single-Chip Mode Mode 3 Port Port 5 Description * 6-bit I/O port Pins P55/SCK1 P54/RxD1 P53/TxD1 P52/SCK0 P51/RxD0 P50/TxD0 P66/IRQ2 P65/IRQ1 P64/IRQ0 P63/FTI/ KEYIN3 P62/FTOB/ KEYIN2 P61/FTOA/ KEYIN1 P60/FTCI/ KEYIN0 Mode 1 Mode 2 Serial communication interface 0 and 1 input/output (TxD0, RxD0, SCK 0, TxD1, RxD1, SCK 1) or 6-bit general input/output Port 6 * 7-bit I/O port * Built-in input pull-ups (P63 to P60) IRQ2 to IRQ0 or general input/output 16-bit free-running timer input/output (FTCI, FTOA, FTOB, FTI) or general input/output (Can also be used as key-scanning key-sense input (KEYIN3 to KEYIN0)) Port 7 * 8-bit I/O port * Bus buffer drive capability (P73 to P7 0) * Built-in input pull-ups (P73 to P70) P77/WAIT/ Expanded data bus control input/ HA 0 output (WAIT, RD, WR, AS) P76/RD/IOR P75/WR/IOW P74/AS/CS 1 Host interface control input (HA0, IOR, IOW, CS 1) or general input/output P73/KEYIN7 P72/KEYIN6 P71/KEYIN5 P70/KEYIN4 General input/output (Can also be used as key-scanning key-sense input (KEYIN7 to KEYIN4)) 97 7.2 7.2.1 Port 1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. Port 1 has built-in programmable MOS input pull-ups that can be used in modes 2 and 3. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and Darlington transistors. Port 1 pins P17/A7 P16/A6 P15/A5 Port 1 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A7 (output)/P17 (input) A6 (output)/P16 (input) A5 (output)/P15 (input) A4 (output)/P14 (input) A3 (output)/P13 (input) A2 (output)/P12 (input) A1 (output)/P11 (input) A0 (output)/P10 (input) Pin configuration in mode 3 (single-chip mode) P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7-1 Port 1 Pin Configuration 98 7.2.2 Register Configuration and Descriptions Table 7-2 summarizes the port 1 registers. Table 7-2 Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Port 1 Registers Abbreviation P1DDR P1DR P1PCR Read/Write W R/W R/W Initial Value Address H'FF (mode 1) H'FFB0 H'00 (modes 2 and 3) H'00 H'00 H'FFB2 H'FFAC Port 1 Data Direction Register (P1DDR) Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P1DDR controls the input/output direction of each pin in port 1. Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P1DDR bit is set to 1, the corresponding pin remains in the output state. 99 Port 1 Data Register (P1DR) Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if port 1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR bit is cleared to 0, if port 1 is read the pin state is obtained. P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 1 Input Pull-Up Control Register (P1PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P1PCR is an 8-bit readable/writable register that controls the MOS input pull-ups in port 1. If a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the MOS input pull-up is turned on. P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 100 7.2.3 Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is automatically used for lower address output (A7 to A0). Figure 7-2 shows the pin functions in mode 1. A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 7-2 Pin Functions in Mode 1 (Port 1) 101 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins, and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output or PWM output, their P1DDR bits must be set to 1. Figure 7-3 shows the pin functions in mode 2. When P1DDR = 1 A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When P1DDR = 0 P17 (input) P16 (input) P15 (input) P14 (input) P13 (input) P12 (input) P11 (input) P10 (input) Figure 7-3 Pin Functions in Mode 2 (Port 1) 102 Mode 3: In mode 3 (single-chip mode), port 1 can provide general input/output pins. When used for general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0. When this bit is set to 1, the corresponding pin becomes a general output pin. Figure 7-4 shows the pin functions in mode 3. When P1DDR = 0 (input pin) and when P1DDR = 1 (output pin) P17 (input/output) P16 (input/output) P15 (input/output) Port 1 P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7-4 Pin Functions in Mode 3 (Port 1) 7.2.4 MOS Input Pull-Ups Port 1 has built-in programmable MOS input pull-ups that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-3 indicates the states of the MOS input pull-ups in each operating mode. Table 7-3 Mode 1 2 3 States of MOS Input Pull-Ups (Port 1) Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off Notes: Off: The MOS input pull-up is always off. On/off: The MOS input pull-up is on if P1PCR = 1 and P1DDR = 0, but off otherwise. 103 7.3 7.3.1 Port 2 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-5. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-ups that can be used in modes 2 and 3. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and Darlington transistors. Port 2 pins P27/A15 P26/A14 P25/A13 Port 2 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A15 (output)/P27 (input) A14 (output)/P26 (input) A13 (output)/P25 (input) A12 (output)/P24 (input) A11 (output)/P23 (input) A10 (output)/P22 (input) A9 (output)/P21 (input) A8 (output)/P20 (input) Pin configuration in mode 3 (single-chip mode) P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7-5 Port 2 Pin Configuration 104 7.3.2 Register Configuration and Descriptions Table 7-4 summarizes the port 2 registers. Table 7-4 Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Port 2 Registers Abbreviation P2DDR P2DR P2PCR Read/Write W R/W R/W Initial Value Address H'FF (mode 1) H'FFB1 H'00 (modes 2 and 3) H'00 H'00 H'FFB3 H'FFAD Port 2 Data Direction Register (P2DDR) Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P2DDR controls the input/output direction of each pin in port 2. Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P2DDR bit is set to 1, the corresponding pin remains in the output state. 105 Port 2 Data Register (P2DR) Bit Initial value Read/Write 7 P2 7 0 R/W 6 P2 6 0 R/W 5 P2 5 0 R/W 4 P2 4 0 R/W 3 P2 3 0 R/W 2 P2 2 0 R/W 1 P2 1 0 R/W 0 P2 0 0 R/W P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if port 2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR bit is cleared to 0, if port 2 is read the pin state is obtained. P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 2 Input Pull-Up Control Register (P2PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P2PCR is an 8-bit readable/writable register that controls the MOS input pull-ups in port 2. If a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the MOS input pull-up is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 106 7.3.3 Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is automatically used for upper address output (A15 to A8). Figure 7-6 shows the pin functions in mode 1. A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 7-6 Pin Functions in Mode 1 (Port 2) 107 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins, and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7-7 shows the pin functions in mode 2. When P2DDR = 1 A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When P2DDR = 0 P27 (input) P26 (input) P25 (input) P24 (input) P23 (input) P22 (input) P21 (input) P20 (input) Figure 7-7 Pin Functions in Mode 2 (Port 2) 108 Mode 3: In mode 3 (single-chip mode) port 2 can provide general input/output pins. When used for general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0. When this bit is set to 1, the corresponding pin becomes a general output pin. Figure 7-8 shows the pin functions in mode 3. When P2DDR = 0 (input pin) and when P2DDR = 1 (output pin) P27 (input/output) P26 (input/output) P25 (input/output) Port 2 P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7-8 Pin Functions in Mode 3 (Port 2) 109 7.3.4 MOS Input Pull-Ups Port 2 has built-in programmable MOS input pull-ups that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-5 indicates the states of the input pull-up transistors in each operating mode. Table 7-5 Mode 1 2 3 States of MOS Input Pull-Ups (Port 2) Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off Notes: Off: The MOS input pull-up is always off. On/off: The MOS input pull-up is on if P2PCR = 1 and P2DDR = 0, but off otherwise. 110 7.4 7.4.1 Port 3 Overview Port 3 is an 8-bit input/output port that is multiplexed with the data bus and host interface data bus. Its pin configuration is shown in figure 7-9. The pin functions differ depending on the operating mode. Port 3 has built-in programmable MOS input pull-ups that can be used in mode 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a LED and a Darlington transistor. Port 3 pins P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 Port 3 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0 Pin configuration in mode 3 (single-chip mode) Master mode P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Pin configuration in mode 3 (single-chip mode) Slave mode HDB7 (input/output) HDB6 (input/output) HDB5 (input/output) HDB4 (input/output) HDB3 (input/output) HDB2 (input/output) HDB1 (input/output) HDB0 (input/output) Figure 7-9 Port 3 Pin Configuration 111 7.4.2 Register Configuration and Descriptions Table 7-6 summarizes the port 3 registers. Table 7-6 Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Port 3 Registers Abbreviation P3DDR P3DR P3PCR Read/Write W R/W R/W Initial Value H'00 H'00 H'00 Address H'FFB4 H'FFB6 H'FFAE Port 3 Data Direction Register (P3DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR P3DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 3. P3DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored. Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0). The data bus is in the high-impedance state during reset, and during hardware and software standby. Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output state. 112 Port 3 Data Register (P3DR) Bit Initial value Read/Write 7 P3 7 0 R/W 6 P3 6 0 R/W 5 P3 5 0 R/W 4 P3 4 0 R/W 3 P3 3 0 R/W 2 P3 2 0 R/W 1 P3 1 0 R/W 0 P3 0 0 R/W P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port 3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR bit is cleared to 0, if port 3 is read the pin state is obtained. P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 3 Input Pull-Up Control Register (P3PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P3PCR is an 8-bit readable/writable register that controls the MOS input pull-ups in port 3. If a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the MOS input pull-up is turned on. P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. The MOS input pull-ups cannot be used in slave mode (when the host interface is enabled). 113 7.4.3 Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the input/output pins of the data bus (D7 to D0). Figure 7-10 shows the pin functions in modes 1 and 2. Modes 1 and 2 D7 (input/output) D6 (input/output) D5 (input/output) Port 3 D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 7-10 Pin Functions in Modes 1 and 2 (Port 3) 114 Mode 3: In mode 3 (single-chip mode), port 3 is an input/output port when the host interface enable bit (HIE) in the system control register (SYSCR) is cleared to 0. If the HIE bit is set to 1 and a transition is made to slave mode, port 3 becomes the host interface data bus (HDB7 to HDB0). In slave mode, P3DR and P3DDR should be cleared to H'00. Figure 7-11 shows the pin functions in mode 3. P37 (input/output)/HDB7 (input/output) P36 (input/output)/HDB6 (input/output) P35 (input/output)/HDB5 (input/output) Port 3 P34 (input/output)/HDB4 (input/output) P33 (input/output)/HDB3 (input/output) P32 (input/output)/HDB2 (input/output) P31 (input/output)/HDB1 (input/output) P30 (input/output)/HDB0 (input/output) Figure 7-11 Pin Functions in Mode 3 (Port 3) 7.4.4 Input Pull-Up Transistors Port 3 has built-in programmable MOS input pull-ups that are available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set the corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-7 indicates the states of the input MOS pull-ups in each operating mode. Table 7-7 Mode 1 2 3 States of MOS Input Pull-Ups (Port 3) Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off Notes: Off: The MOS input pull-up is always off. On/off: The MOS input pull-up is on if P3PCR = 1 and P3DDR = 0, but off otherwise. 115 7.5 7.5.1 Port 4 Overview Port 4 is an 8-bit input/output port that is multiplexed with the host interface (HIF) input/output pins (GA20, CS2), host interrupt request output pins (HIRQ12, HIRQ1, HIRQ11), 8-bit timer 0, and 1, and input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) and the o clock output pin. Pins P47 and P45 to P40 have the same functions in all operating modes, but the slave mode function which enables the host interface is only valid in single-chip mode. The function of pin P4 6 differs depending on the operating mode. Figure 7-12 shows the pin configuration of port 4. Pins in port 4 (except P4 6) can drive one TTL load and a 30-pF capacitive load. The o clock output pin can drive one TTL load and a 90-pF capacitive load. Port 4 pins can also drive a Darlington transistor. Port 4 pins P47/GA20 P46/o/CS2 P45/TMRI1/HIRQ12 Port 4 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0 P41/TMO0 P40/TMCI0 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P47 (input/output) o (output) P45 (input/output)/TMRI1 (input) P44 (input/output)/TMO1 (output) P43 (input/output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) Pin configuration in mode 3 (single-chip mode) Master mode P47 (input/output) P46 (input)/o (output) P45 (input/output)/TMRI1 (input) P44 (input/output)/TMO1 (output) P43 (input/output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) Pin configuration in mode 3 (single-chip mode) Slave mode P47 (input/output)/GA20 (output) CS2 (input) P45 (input)/HIRQ12 (output)/TMRI1 (input) P44 (input)/HIRQ1 (output)/TMO1 (output) P43 (input)/HIRQ11 (output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) Figure 7-12 Port 4 Pin Configuration 116 7.5.2 Register Configuration and Descriptions Table 7-8 summarizes the port 4 registers. Table 7-8 Name Port 4 data direction register Port 4 data register Notes: 1. 2. Port 4 Registers Abbreviation P4DDR P4DR Read/Write W R/W*1 Initial Value H'40 (mode 1 and 2) H'00 (mode 3) Undetermined *2 Address H'FFB5 H'FFB7 Bit 6 is read-only. Bit 6 only is undetermined; the other bits are 0. Port 4 Data Direction Register (P4DDR) Bit Mode 1 and 2 Initial value Read/Write Mode 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 7 6 5 4 3 2 1 0 P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit is cleared to 0. However, in modes 1 and 2, P46DDR is fixed at 1 and cannot be modified. P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P4DDR is initialized--to H'40 in modes 1 and 2, and to H'00 in mode 3--by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 4 is being used by an on-chip supporting module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR. 117 Port 4 Data Register (P4DR) Bit Initial value Read/Write 7 P4 7 0 R/W 6 P4 6 * R 5 P4 5 0 R/W 4 P4 4 0 R/W 3 P4 3 0 R/W 2 P4 2 0 R/W 1 P4 1 0 R/W 0 P4 0 0 R/W Note: * Depends on the state of the P46 pin. P4DR is an 8-bit register that stores data for port 4 pins P47 to P40. With the exception of P46, when a P4DDR bit is set to 1, if port 4 is read, the value in P4DR is obtained directly. When a P4DDR bit is cleared to 0, if port 4 is read the pin state is obtained. When P46 is read, the pin state is always obtained. This also applies to the clock output pin and pins used by the on-chip supporting modules. P4DR bits other than P46 are initialized to 0 by a reset and in hardware standby mode. In software standby mode, P4DR retains its values prior to the mode transition. 118 7.5.3 Pin Functions Port 4 pins are used for 8-bit timer and host interface input/output and oclock output. Table 7-9 indicates the pin functions of port 4. Table 7-9 Pin P47/GA 20 Port 4 Pin Functions Pin Functions and Selection Method Bit FGA20E in HICR, bit P4 7DDR, and the operating mode select the pin function as follows P47DDR FGA20E Operating mode Pin function 0 -- -- P47 input 0 -- Other than slave mode P47 output 1 1 Slave mode GA20 output P46/o/CS2 Bit P46DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 -- P46DDR Pin function -- o clock output Mode 3 Other than slave mode 0 P46 input 1 o clock output Slave mode -- CS 2 input P45/TMRI1/ HIRQ12 P45DDR Operating mode Pin function 0 -- P45 input Other than slave mode P45 output TMRI1 input 1 Slave mode HIRQ12 output TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 119 Table 7-9 Pin P44/TMO1/ HIRQ1 Port 4 Pin Functions (cont) Pin Functions and Selection Method Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit P4 4DDR, and the operating mode select the pin function as follows OS3 to OS0 P44DDR Operating mode Pin function 0 -- P44 input Other than slave mode P44 output All 0 1 Slave mode HIRQ1 output Not all 0 -- -- TMO1 output P43/TMCI1/ HIRQ11 P43DDR Operating mode Pin function 0 -- P43 input Other than slave mode P43 output TMCI1 input 1 Slave mode HIRQ11 output TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source P42/TMRI0 P42DDR Pin function 0 P42 input TMRI0 input 1 P42 output TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 0 120 Table 7-9 Pin P41/TMO0 Port 4 Pin Functions (cont) Pin Functions and Selection Method Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P4 1DDR select the pin function as follows OS3 to OS0 P41DDR Pin function 0 P41 input All 0 1 P41 output Not all 0 -- TMO0 output P40/TMCI0 P40DDR Pin function 0 P40 input TMCI0 input 1 P40 output TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source 121 7.6 7.6.1 Port 5 Overview Port 5 is a 6-bit input/output port that is multiplexed with input/output pins (TxD 0, RxD0, SCK0, TxD1, RxD1, SCK1) of serial communication interfaces 0 and 1. The port 5 pin functions are the same in all operating modes. Figure 7-13 shows the pin configuration of port 5. Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington transistor. Port 5 pins P55 (input/output)/SCK1 (input/output) P54 (input/output)/RxD1 (input) Port 5 P53 (input/output)/TxD1 (output) P52 (input/output)/SCK0 (input/output) P51 (input/output)/RxD0 (input) P50 (input/output)/TxD0 (output) Figure 7-13 Port 5 Pin Configuration 7.6.2 Register Configuration and Descriptions Table 7-10 summarizes the port 5 registers. Table 7-10 Port 5 Registers Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR Read/Write W R/W Initial Value H'C0 H'C0 Address H'FFB8 H'FFBA 122 Port 5 Data Direction Register (P5DDR) 7 Bit Initial value Read/Write -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P5DDR is a write-only register. Read data is invalid. Bits 7 and 6 are reserved. If read, all bits always read 1. P5DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and P5DR. Port 5 Data Register (P5DR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W P5DR is an 8-bit register that stores data for pins P55 to P50. Bits 7 and 6 are reserved. They cannot be modified, and are always read as 1. When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained. This also applies to pins used as SCI pins. P5DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 123 7.6.3 Pin Functions Port 5 has the same pin functions in each operating mode. Individual pins can also be used as SCI0 or SCI1 input/output pins. Table 7-11 indicates the pin functions of port 5. Table 7-11 Port 5 Pin Functions Pin P55/SCK1 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P55DDR select the pin function as follows CKE1 C/A CKE0 P55DDR Pin function 0 P55 input 0 1 P55 output 0 1 -- SCK 1 output 0 1 -- -- SCK 1 output 1 -- -- -- SCK 1 input P54/RxD1 Bit RE in SCR of SCI1 and bit P54DDR select the pin function as follows RE P54DDR Pin function 0 P54 input 0 1 P54 output 1 -- RxD1 input P53/TxD1 Bit TE in SCR of SCI1 and bit P53DDR select the pin function as follows TE P53DDR Pin function 0 P53 input 0 1 P53 output 1 -- TxD1 output 124 Table 7-11 Port 5 Pin Functions (cont) Pin P52/SCK0 Pin Functions and Selection Method Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0 and bit P5 2DDR select the pin function as follows CKE1 C/A CKE0 P52DDR Pin function 0 P52 input 0 1 P52 output 0 1 -- SCK 0 output 0 1 -- -- SCK 0 output 1 -- -- -- SCK 0 input P51/RxD0 Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows RE P51DDR Pin function 0 P51 input 0 1 P51 output 1 -- RxD0 input P50/TxD0 Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows TE P50DDR Pin function 0 P50 input 0 1 P50 output 1 -- TxD0 output 125 7.7 7.7.1 Port 6 Overview Port 6 is a 7-bit input/output port that is multiplexed with 16-bit free-running timer (FRT) input/output pins (FTCI, FTOA, FTOB, FTI), key-sense input pins and with IRQ0 to IRQ2 input pins. The port 6 pin functions are the same in all operating modes. Pins P60 to P63 in port 6 have program-controllable built-in MOS pull-ups. Figure 7-14 shows the pin configuration of port 6. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor. Port 6 pins P66 (input/output)/IRQ2 (input) P65 (input/output)/IRQ1 (input) P64 (input/output)/IRQ0 (input) Port 6 P63 (input/output)/FTI (input)/KEYIN3 (input) P62 (input/output)/FTOB (output)/KEYIN2 (input) P61 (input/output)/FTOA (output)/KEYIN1 (input) P60 (input/output)/FTCI (input)/KEYIN0 (input) Figure 7-14 Port 6 Pin Configuration 126 7.7.2 Register Configuration and Descriptions Table 7-12 summarizes the port 6 registers. Table 7-12 Port 6 Registers Name Port 6 data direction register Port 6 data register Key-sense MOS pull-up control register Abbreviation P6DDR P6DR KMPCR Read/Write W R/W R/W Initial Value H'80 H'80 H'00 Address H'FFB9 H'FFBB H'FFF2 Port 6 Data Direction Register (P6DDR) Bit Initial value Read/Write 7 -- 1 -- 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P6DDR is a write-only register. Read data is invalid. Bit 7 is reserved. If read, all bits always read 1. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 6 is being used by an on-chip supporting module (for example, the free-running timer), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P6DDR and P6DR. 127 Port 6 Data Register (P6DR) Bit Initial value Read/Write 7 -- 1 -- 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W P6DR is an 8-bit register that stores data for pins P66 to P60. Bit 7 is reserved; it cannot be modified and is always read as 1. When a P6DDR bit is set to 1, if port 6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used by the on-chip supporting modules. P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its existing values. When a port P6DDR bit is cleared to 0, if port 6 is read, the pin state is obtained; this pin can be selected according to the contents of KMIMR7 to KMIMR4. When KMIMR is set to 1 (initial value), empty bit 7, pins P66, P65, and P64 are selected. When KMIMR is cleared to 0, pins P73, P7 2, P7 1, and P70 are selected, respectively, corresponding to KMIMR7, KMIMR6, KMIMR5, and KMIMR4. Key-Sense MOS Pull-Up Control Register (KMPCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR KMPCR is an 8-bit readable/writable register that controls the port 6 and port 7 built-in MOS pullups on a bit-by-bit basis. When a P6DDR or P7DDR bit is cleared to 0 (input port state), if the corresponding KMPCR bit is set to 1 the MOS pull-up is turned on. KM7PCR to KM4PCR correspond to P73DDR to P70DDR and pins P73 to P70, while KM3PCR to KM0PCR correspond to P63DDR to P60DDR and pins P63 to P60. KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 128 7.7.3 Pin Functions Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT input/output, key-sense input, and IRQ0 to IRQ2 input. Table 7-13 indicates the pin functions of port 6. Table 7-13 Port 6 Pin Functions Pin (P67) Pin Functions and Selection Method KMIMR7 Pin function 0 P73 pin input function in a P67DR read 1 1 input in a P6 7DR read P66/IRQ2 P66DDR KMIMR6 Pin function 0 P72 pin input function in a P6 6DR read 0 1 P66 input 1 -- P66 output IRQ2 input IRQ2 input is usable when bit IRQ2E is set to 1 in IER P65/IRQ1 P65DDR KMIMR5 Pin function 0 P71 pin input function in a P6 5DR read 0 1 P65 input 1 -- P65 output IRQ1 input IRQ1 input is usable when bit IRQ1E is set to 1 in IER P64/IRQ0 P64DDR KMIMR4 Pin function 0 P70 pin input function in a P6 4DR read 0 1 P64 input 1 -- P64 output IRQ0 input IRQ0 input is usable when bit IRQ0E is set to 1 in IER 129 Table 7-13 Port 6 Pin Functions (cont) Pin P63/FTI/KEYIN3 Pin Functions and Selection Method P63DDR Pin function 0 P63 input 1 P63 output FTI input, or KEYIN3 input P62/FTOB/ KEYIN2 Bit OEB in TCR of the FRT, and the P62DDR bit select the pin function as follows OEB P62DDR Pin function 0 P62 input 0 1 P62 output KEYIN2 input P61/FTOA/ KEYIN1 Bit OEA in TCR of the FRT and bit P6 1DDR select the pin function as follows OEA P61DDR Pin function 0 P61 input 0 1 P61 output KEYIN1 input 1 -- FTOA output 1 -- FTOB output P60/FTCI/ KEYIN0 P60DDR Pin function 0 P60 input 1 P60 output FTCI input or KEYIN0 input FTCI input is usable when bits CKS1 and CKS0 in TCR of the FRT select an external clock source 130 7.8 7.8.1 Port 7 Overview Port 7 is an 8-bit input/output port that also provides the bus control signal input/output pins (RD, WR, AS, WAIT), host interface (HIF) input pins (HA0, IOR, IOW, CS1), and key-sense input pins. The functions of pins P77 to P74 differ depending on the operating mode. Pins P70 to P73 have program-controllable built-in MOS pull-ups. Figure 7-15 shows the pin configuration of port 7. Pins in port 7 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor. Port 7 pins P77/WAIT/HA0 P76/RD/IOR P75/WR/IOW Port 7 P74/AS/CS1 P73/KEYIN7 P72/KEYIN6 P71/KEYIN5 P70/KEYIN4 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) WAIT (input)/P77 (input) RD (output) WR (output) AS (output) P73 (input/output)/KEYIN7 (input) P72 (input/output)/KEYIN6 (input) P71 (input/output)/KEYIN5 (input) P70 (input/output)/KEYIN4 (input) Pin configuration in mode 3 (single-chip mode) Master mode P77 (input/output) P76 (input/output) P75 (input/output) P74 (input/output) P73 (input/output)/KEYIN7 (input) P72 (input/output)/KEYIN6 (input) P71 (input/output)/KEYIN5 (input) P70 (input/output)/KEYIN4 (input) Pin configuration in mode 3 (single-chip mode) Slave mode HA0 (input) IOR (input) IOW (input) CS1 (input) P73 (input/output)/KEYIN7 (input) P72 (input/output)/KEYIN6 (input) P71 (input/output)/KEYIN5 (input) P70 (input/output)/KEYIN4 (input) Figure 7-15 Port 7 Pin Configuration 131 7.8.2 Register Configuration and Descriptions Table 7-15 summarizes the port 7 registers. Table 7-15 Port 7 Registers Name Port 7 data direction register Port 7 data register Key-sense MOS pull-up control register Abbreviation P7DDR P7DR KMPCR Read/Write W R/W R/W Initial Value H'00 H'00 H'00 Address H'FFBC H'FFBE H'FFF2 Port 7 Data Direction Register (P7DDR) 7 Bit Initial value Read/Write 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 1 W P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR P7DDR is an 8-bit register that controls the input/output direction of each pin in port 7. A pin functions as an output pin if the corresponding P7DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P7DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P7DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode P7DDR retains its existing values, so if a transition to software standby mode occurs while a P7DDR bit is set to 1, the corresponding pin remains in the output state. Port 7 Data Register (P7DR) Bit Initial value Read/Write 7 P77 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W P7DR is an 8-bit register that stores data for pins P77 to P70. When a P7DDR bit is set to 1, if port 7 is read, the value in P7DR is obtained directly, regardless of the actual pin state. When a P7DDR bit is cleared to 0, if port 7 is read the pin state is obtained. P7DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 132 When a port P6DDR bit is cleared to 0, if port 6 is read, the pin state is obtained; this pin can be selected according to the contents of KMIMR7 to KMIMR4. When KMIMR is set to 1 (initial value), bit 7 is an empty bit, and pins P66, P65, and P64 are selected. When KMIMR is cleared to 0, pins P73, P7 2, P7 1, and P70 are selected, respectively, corresponding to KMIMR7, KMIMR6, KMIMR5, and KMIMR4. Key-Sense MOS Pull-Up Control Register (KMPCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR KMPCR is an 8-bit readable/writable register that controls the port 6 and port 7 built-in MOS pullups on a bit-by-bit basis. When a P6DDR or P7DDR bit is cleared to 0 (input port state), if the corresponding KMPCR bit is set to 1 the MOS pull-up is turned on. KM7PCR to KM4PCR correspond to P73DDR to P70DDR and pins P73 to P70, while KM3PCR to KM0PCR correspond to P63DDR to P60DDR and pins P63 to P60. KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 133 7.8.3 Pin Functions The pins of port 7 have different functions in modes 1 and 2 and in mode 3. Individual pins are used as bus control signal input/output pins (RD, WR, AS, WAIT), host interface (HIF) input pins (HA0, IOR, IOW, CS1), and key-sense input pins. Table 7-19 indicates the pin functions of port 7. Table 7-16 Port 7 Pin Functions Pin P77/WAIT/HA0 Pin Functions and Selection Method Bit P77DDR, the wait mode determined by WSCR, and the operating mode select the pin function as follows Operating mode Modes 1 and 2 -- Wait mode P77DDR Pin function WAIT used -- WAIT input WAIT not used 0 P77 input 1 -- 0 P77 input Mode 3 Other than slave mode -- 1 P77 output -- HA 0 input Slave mode P76/RD/IOR Bit P76DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 -- P76DDR Pin function -- RD output Mode 3 Other than slave mode 0 P76 input 1 P76 output Slave mode -- IOR input P75/WR/IOW Bit P75DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 -- P75DDR Pin function -- WR output Mode 3 Other than slave mode 0 P75 input 1 P75 output Slave mode -- IOW input 134 Table 7-16 Port 7 Pin Functions (cont) Pin P74/AS/CS 1 Pin Functions and Selection Method Bit P74DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 -- P74DDR Pin function -- AS output Mode 3 Other than slave mode 0 P74 input 1 P74 output Slave mode -- CS 1 input P73/KEYIN7 Bit P73DDR select the pin function as follows P73DDR Pin function 0 P73 input KEYIN7 input 1 P73 output P72/KEYIN6 Bit P72DDR select the pin function as follows P72DDR Pin function 0 P72 input KEYIN6 input 1 P72 output P71 Bit P71DDR select the pin function as follows P71DDR Pin function 0 P71 input KEYIN5 input 1 P71 output P70 Bit P70DDR select the pin function as follows P70DDR Pin function 0 P70 input KEYIN4 input 1 P70 output 135 136 Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3502 has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit freerunning counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 8.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (oP/2, oP/8, or oP/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Input capture The current count can be captured on the rising or falling edge (selectable) of an input signal. * Counter can be cleared under program control The free-running counter can be cleared on compare-match A. * Four interrupt sources Compare-match A and B, input capture, and overflow interrupts are requested independently. 137 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the free-running timer. External clock source FTCI Clock select Internal clock sources oP/2 oP/8 oP/32 Clock Comparematch A OCRA (H/L) Comparator A FTOA FTOB FTI Overflow Clear Comparator B Bus interface FRC (H/L) Internal data bus Comparematch B Control logic Capture OCRB (H/L) ICR (H/L) TCSR TCR ICI OCIA OCIB FOVI Interrupt signals Legend OCRA: OCRB: FRC: ICR: TCSR: TCR: Output compare register A Output compare register B Free-running counter Input capture register Timer control/status register Timer control register Figure 8-1 Block Diagram of 16-Bit Free-Running Timer 138 Module data bus 8.1.3 Input and Output Pins Table 8-1 lists the input and output pins of the free-running timer module. Table 8-1 Name Counter clock input Output compare A Output compare B Input capture Input and Output Pins of Free-Running Timer Module Abbreviation FTCI FTOA FTOB FTI I/O Input Output Output Input Function Input of external free-running counter clock signal Output controlled by comparator A Output controlled by comparator B Input capture trigger 8.1.4 Register Configuration Table 8-2 lists the registers of the free-running timer module. Table 8-2 Name Timer control register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A (high) Output compare register A (low) Output compare register B (high) Output compare register B (low) Input capture register (high) Input capture register (low) Register Configuration Abbreviation TCR TCSR FRC (H) FRC (L) OCRA (H) OCRA (L) OCRB (H) OCRB (L) ICR (H) ICR (L) R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R R Initial Value H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 Note: * Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits. 139 8.2 8.2.1 Bit Register Descriptions Free-Running Counter (FRC)--H'FF92 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written or read. See section 8.3, CPU Interface, for details. The FRC is initialized to H'0000 by a reset and in the standby modes. 8.2.2 Bit Initial value Output Compare Registers A and B (OCRA and OCRB)--H'FF94 and H'FF96 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set to 1 in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer output compare control register (TCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). After a reset, the output of FTOA and FTOB is 0 until the first compare-match event. Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used for write access, as explained in section 8.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes. 140 8.2.3 Bit Input Capture Register (ICR)--H'FF98 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The input capture register is a 16-bit read-only register. When the rising or falling edge of the signal at the input capture pin (FTI) is detected, the current value of the FRC is copied to the input capture register (ICR). At the same time, the input capture flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bit (IEDG) in the TCSR. Because the input capture register is a 16-bit register, a temporary register (TEMP) is used when it is read. See Section 8.3, CPU Interface, for details. To ensure input capture, the width of the input capture pulse (FTI) should be at least 1.5 system clock cycles (1.5 o). The input capture register is initialized to H'0000 by a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the input capture register even if the input capture flag is already set. 141 8.2.4 Bit Timer Control Register (TCR)--H'FF90 7 ICIE 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write TCR is an 8-bit readable/writable register that enables and disables output signals and interrupts, and selects the timer clock source. TCR is initialized to H'00 by a reset and in the standby modes. Bit 7--Input Capture Interrupt Enable (ICIE): Selects whether to request an input capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register (TCSR) is set to 1. Bit 7 ICIE 0 1 Description Input capture interrupt request (ICI) is disabled Input capture interrupt request (ICI) is enabled (Initial value) Bit 6--Output Compare Interrupt Enable B (OCIEB): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control register (TCSR) is set to 1. Bit 6 OCIEB 0 1 Description Output compare interrupt request B (OCIB) is disabled Output compare interrupt request B (OCIB) is enabled (Initial value) Bit 5--Output Compare Interrupt Enable A (OCIEA): Selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control register (TCSR) is set to 1. Bit 5 OCIEA 0 1 Description Output compare interrupt request A (OCIA) is disabled Output compare interrupt request A (OCIA) is enabled (Initial value) 142 Bit 4--Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer status/control register (TCSR) is set to 1. Bit 4 OVIE 0 1 Description Timer overflow interrupt request (FOVI) is disabled Timer overflow interrupt request (FOVI) is enabled (Initial value) Bit 3--Output Enable B (OEB): Enables or disables output of the output compare B signal (FTOB). If output compare B is enabled, the FTOB pin is driven to the level selected by OLVLB in the timer status/control register (TCSR) whenever the FRC value matches the value in output compare register B (OCRB). Bit 3 OEB 0 1 Description Output compare B output is disabled Output compare B output is enabled (Initial value) Bit 2--Output Enable A (OEA): Enables or disables output of the output compare A signal (FTOA). If output compare A is enabled, the FTOA pin is driven to the level selected by OLVLA in the timer status/control register (TCSR) whenever the FRC value matches the value in output compare register A (OCRA). Bit 2 OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (Initial value) Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge at the external clock pin (FTCI). Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description oP/2 internal clock source oP/8 internal clock source oP/32 internal clock source External clock source (rising edge) 143 (Initial value) 8.2.5 Bit Timer Control/Status Register (TCSR)--H'FF91 7 ICF 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)* 3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W 0 CCLRA 0 R/W Initial value Read/Write Note: * Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable register that contains four status flags and selects the output compare levels, input capture edge, and whether to clear the counter on compare-match A. TCSR is initialized to H'00 by a reset and in the standby modes. Bit 7--Input Capture Flag (ICF): This status flag is set to 1 to indicate an input capture event, showing that the FRC value has been copied to the ICR. ICF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 ICF 0 1 Description To clear ICF, the CPU must read ICF after it has been set to 1, then write a 0 in this bit This bit is set to 1 when an FTI input signal causes the FRC value to be copied to the ICR (Initial value) Bit 6--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. OCFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 OCFB 0 1 Description To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit This bit is set to 1 when FRC = OCRB (Initial value) 144 Bit 5--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. OCFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 OCFA 0 1 Description To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit This bit is set to 1 when FRC = OCRA (Initial value) Bit 4--Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 4 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit This bit is set to 1 when FRC changes from H'FFFF to H'0000 (Initial value) Bit 3--Output Level B (OLVLB): Selects the logic level output at the FTOB pin when the FRC and OCRB values match. Bit 3 OLVLB 0 1 Description A 0 logic level is output for compare-match B A 1 logic level is output for compare-match B (Initial value) Bit 2--Output Level A (OLVLA): Selects the logic level output at the FTOA pin when the FRC and OCRA values match. Bit 2 OLVLA 0 1 Description A 0 logic level is output for compare-match A A 1 logic level is output for compare-match A (Initial value) 145 Bit 1--Input Edge Select (IEDG): Selects the rising or falling edge of the input capture signal (FTI). Bit 1 IEDG 0 1 Description FRC contents are transferred to ICR on the falling edge of FTI FRC contents are transferred to ICR on the rising edge of FTI (Initial value) Bit 0--Counter Clear A (CCLRA): Selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA 0 1 Description The FRC is not cleared The FRC is cleared at compare-match A (Initial value) 146 8.3 CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture register (ICR) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows: * Register write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. (As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP.) Programs that access these registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be transferred correctly if the bytes are accessed in reverse order, if only one byte is accessed, or if the upper and lower bytes are accessed separately and another register is accessed in between, altering the value in TEMP. Coding Examples To write the contents of general register R0 to OCRA: To transfer the ICR contents to general register R0: MOV.W MOV.W R0, @OCRA @ICR, R0 Figure 8-2 shows the data flow when the FRC is accessed. The other registers are accessed in the same way. 147 (1) Upper byte write Module data bus CPU writes data H'AA Bus interface TEMP [H'AA] FRCH [ ] (2) Lower byte write FRCL [ ] CPU writes data H'55 Bus interface Module data bus TEMP [H'AA] FRCH [H'AA] FRCL [H'55] Figure 8-2 (a) Write Access to FRC (When CPU Writes H'AA55) 148 (1) Upper byte read CPU writes data H'AA Bus interface Module data bus TEMP [H'55] FRCH [H'AA] FRCL [H'55] (2) Lower byte read Module data bus CPU writes data H'55 Bus interface TEMP [H'55] FRCH [ ] FRCL [ ] Figure 8-2 (b) Read Access to FRC (When FRC Contains H'AA55) 149 8.4 8.4.1 Operation FRC Incrementation Timing The FRC increments on a pulse generated once for each cycle of the selected (internal or external) clock source. (1) Internal Clock Sources: Can be selected by the CKS1 and CKS0 bits in TCR. Internal clock sources are created by dividing the system clock (o). Three internal clock sources are available: oP/2, oP/8, and oP/32. Figure 8-3 shows the increment timing. o Internal clock FRC clock pulse FRC N-1 N N+1 Figure 8-3 Increment Timing for Internal Clock Source 150 (2) External Clock Input: Can be selected by the CKS1 and CKS0 bits in the TCR. The FRC increments on the rising edge of the FTCI clock signal. The pulse width of the external clock signal must be at least 1.5 system clock (o) cycles. The counter will not increment correctly if the pulse width is shorter than this. Figure 8-4 shows the increment timing. o External clock input FRC clock pulse FRC N N+1 Figure 8-4 Increment Timing for External Clock Source 151 8.4.2 Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TCSR is output at the output compare pin (FTOA or FTOB). Figure 8-5 shows the timing of this operation for compare-match A. o Internal comparematch A signal Clear* OLVLA FTOA Note: * Cleared by software Figure 8-5 Timing of Output Compare A 8.4.3 FRC Clear Timing If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 8-6 shows the timing of this operation. o Internal comparematch A signal FRC N H'0000 Figure 8-6 Clearing of FRC by Compare-Match A 152 8.4.4 Input Capture Timing An internal input capture signal is generated from the rising or falling edge of the FTI input, as selected by the IEDG bit in TCSR. Figure 8-7 shows the usual input capture timing when the rising edge is selected (IEDG = 1). o Input capture input Internal input capture signal Figure 8-7 Input Capture Timing (Usual Case) If the upper byte of ICR is being read when the internal input capture signal should be generated, the internal input capture signal is delayed by one state. Figure 8-8 shows the timing for this case. ICR upper byte read cycle T1 o T2 T3 Input capture input Internal input capture signal Figure 8-8 Input Capture Timing (1-State Delay Due to ICR Read) 153 8.4.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICF is set to 1 by the internal input capture signal. The FRC contents are transferred to ICR at the same time. Figure 8-9 shows the timing of this operation. o Internal input capture signal ICF FRC N ICR N Figure 8-9 Setting of Input Capture Flag 8.4.6 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when the FRC changes from H'FFFF to H'0000. Figure 8-10 shows the timing of this operation. o FRC H'FFFF H'0000 Internal overflow signal OVF Figure 8-10 Setting of Overflow Flag 154 8.5 Interrupts The free-running timer module can request four types of interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding flag bit is set, provided the corresponding enable bit is also set. Independent signals are sent to the interrupt controller for each type of interrupt. Table 8-3 lists information about these interrupts. Table 8-3 Interrupt ICI OCIA OCIB FOVI Free-Running Timer Interrupts Description Requested when ICF is set Requested when OCFA is set Requested when OCFB is set Requested when OVF is set Low Priority High 8.6 Sample Application In the example below, the free-running timer module is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. The programming is as follows: 1. 2. The CCLRA bit in TCSR is set to 1. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TCSR (OLVLA or OLVLB). 155 FRC H'FFFF OCRA OCRB H'0000 FTOA Clear counter FTOB Figure 8-11 Square-Wave Output (Example) 156 8.7 Application Notes Application programmers should note that the following types of contention can occur in the freerunning timer. (1) Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 8-12 shows this type of contention. FRC lower byte write cycle T1 T2 T3 o Internal address bus Internal write signal FRC address FRC clear signal FRC N H'0000 Figure 8-12 FRC Write-Clear Contention 157 (2) Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and the FRC is not incremented. Figure 8-13 shows this type of contention. FRC lower byte write cycle T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clock pulse FRC N M Write data Figure 8-13 FRC Write-Increment Contention 158 (3) Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the compare-match signal is inhibited. Figure 8-14 shows this type of contention. OCRA or OCRB lower byte write cycle T1 T2 T3 o Intenal address bus OCR address Internal write signal FRC N N+1 OCRA or OCRB N M Write data Compare-match A or B signal Inhibited Figure 8-14 Contention between OCR Write and Compare-Match 159 (4) Increment Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8-4. The pulse that increments the FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case No. 3 in table 8-4, the changeover generates a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock source can also cause the FRC to increment. Table 8-4 No. 1 Effect of Changing Internal Clock Sources Timing Chart Old clock source New clock source FRC clock pulse FRC N CKS rewrite N+1 Description Low low: CKS1 and CKS0 are rewritten while both clock sources are low. 2 Low high: CKS1 and CKS0 are rewritten while old clock source is low and new clock source is high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite 160 Table 8-4 No. 3 Effect of Changing Internal Clock Sources (cont) Timing Chart Old clock source Description High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low. New clock source * FRC clock pulse FRC N N+1 CKS rewrite N+2 4 High high: CKS1 and CKS0 are rewritten while both clock sources are high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite Note: * The switching of clock sources is regarded as a falling edge that increments the FRC. 161 Section 9 8-Bit Timers 9.1 Overview The H8/3502 has an 8-bit timer module with two channels: timers 0 and 1. Each channel has an 8bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty factor. 9.1.1 Features The features of the 8-bit timer module are listed below. * Selection of seven clock sources for TMR0 and TMR1 The counters can be driven by an internal clock signal (selection of six signals for TMR0 and TMR1) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to generate output waveforms with an arbitrary duty factor. PWM mode can be selected, enabling PWM output of 0% to 100%. * Three independent interrupts Compare-match A and B and overflow interrupts can be requested independently. 161 9.1.2 Block Diagram Figure 9-1 shows a block diagram of one channel in the 8-bit timer module. The other channels are identical. External clock source TMCI Internal clock sources Channel 0 oP/2 oP/8 oP/32 oP/64 oP/256 oP/1024 Clock Channel 1 oP/2 oP/8 oP/64 oP/128 oP/1024 oP/2048 Clock select TCORA Compare-match A Comparator A TMO TMRI Clear Comparator B Control logic Compare-match B TCORB Overflow Module data bus TCNT Internal data bus TCSR TCR CMIA CMIB OVI Interrupt signals TCR: TCSR: TCORA: TCORB: TCNT: Timer control register (8 bits) Timer control status register (8 bits) Time constant register A (8 bits) Time constant register B (8 bits) Timer counter Figure 9-1 Block Diagram of 8-Bit Timer (One Channel) 162 Bus interface 9.1.3 Input and Output Pins Table 9-1 lists the input and output pins of the 8-bit timer. Table 9-1 Channel 0 Input and Output Pins of 8-Bit Timer Name Timer output Timer clock input Timer reset input Abbreviation* TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Output controlled by compare-match External clock source for the counter External reset signal for the counter Output controlled by compare-match External clock source for the counter External reset signal for the counter 1 Timer output Timer clock input Timer reset input Note: * The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel number. 9.1.4 Register Configuration Table 9-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 9-2 8-Bit Timer Registers Initial Value H'00 H'00 H'FF H'FF H'00 H'00 Address TMR0 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFC3 TMR1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFC3 Name Timer control register Timer control/status register Timer constant register A Timer constant register B Timer counter Serial timer control register Abbreviation TCR TCSR TCORA TCORB TCNT STCR R/W R/W R/(W)* R/W R/W R/W R/W Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 163 9.2 9.2.1 Bit Register Descriptions Timer Counter (TCNT)--H'FFCC (TMR0), H'FFD4 (TMR1), H'FF9E (TMRX) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from the selected clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter. The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Counter clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counters are initialized to H'00 by a reset and in the standby modes. 9.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1), H'FF9C and H'FF9D (TMRX) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Bit Initial value Read/Write TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers. When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal is controlled by these compare-match signals as specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR). TCORA and TCORB are initialized to H'FF at a reset and in the standby modes. 164 9.2.3 Timer Control Register (TCR)--H'FFC8 (TMR0), H'FFD0 (TMR1), H'FF9A (TMRX) 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit Initial value Read/Write TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. TCR is initialized to H'00 at a reset and in the standby modes. For the timing, see section 9.3, Operation. Bit 7--Compare-Match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status register (TCSR) is set to 1. Bit 7 CMIEB 0 1 Description Compare-match interrupt request B (CMIB) is disabled Compare-match interrupt request B (CMIB) is enabled (Initial value) Bit 6--Compare-Match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer control/status register (TCSR) is set to 1. Bit 6 CMIEA 0 1 Description Compare-match interrupt request A (CMIA) is disabled Compare-match interrupt request A (CMIA) is enabled (Initial value) 165 Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Bit 5 OVIE 0 1 Description The timer overflow interrupt request (OVI) is disabled The timer overflow interrupt request (OVI) is enabled (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input at the TMRI pin. Bit 4 CCLR1 0 0 1 1 Bit 3 CCLR0 0 1 0 1 Description Not cleared Cleared on compare-match A Cleared on compare-match B Cleared on rising edge of external reset input signal (Initial value) 166 Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): Together with the ICKS0 and ICKS1 bits in STCR, these bits select the internal or external clock source for the timer counter. For the external clock source they select whether to increment the count on the rising or falling edge of the external clock input (TMCI), or on both edges. For the internal clock sources the count is incremented on the falling edge of the clock input. TCR Channel 0 Bit 2 CKS2 0 0 0 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 0 1 1 1 1 0 0 1 1 Bit 0 CKS0 0 1 1 0 0 1 1 0 1 0 1 STCR Bit 1 ICKS1 -- -- -- -- -- -- -- -- -- -- -- Bit 0 ICKS0 -- 0 1 0 1 0 1 -- -- -- -- Description No clock source (timer stopped) oP/8 internal clock source, counted on the falling edge oP/2 internal clock source, counted on the falling edge oP/64 internal clock source, counted on the falling edge oP/32 internal clock source, counted on the falling edge oP/1024 internal clock source, counted on the falling edge oP/256 internal clock source, counted on the falling edge No clock source (timer stopped) External clock source, counted on the rising edge External clock source, counted on the falling edge External clock source, counted on both the rising and falling edges 167 TCR Channel 1 Bit 2 CKS2 0 0 0 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 0 1 1 1 1 0 0 1 1 Bit 0 CKS0 0 1 1 0 0 1 1 0 1 0 1 STCR Bit 1 ICKS1 -- 0 1 0 1 0 1 -- -- -- -- Bit 0 ICKS0 -- -- -- -- -- -- -- -- -- -- -- Description No clock source (timer stopped) oP/8 internal clock source, counted on the falling edge oP/2 internal clock source, counted on the falling edge oP/64 internal clock source, counted on the falling edge oP/128 internal clock source, counted on the falling edge oP/1024 internal clock source, counted on the falling edge oP/2048 internal clock source, counted on the falling edge No clock source (timer stopped) External clock source, counted on the rising edge External clock source, counted on the falling edge External clock source, counted on both the rising and falling edges 9.2.4 Timer Control/Status Register (TCSR)--H'FFC9 (TMR0), H'FFD1 (TMR1), H'FF9B (TMRX) 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 PWME 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Bit Initial value Read/Write Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. TCSR is initialized to H'00 at a reset and in the standby modes. 168 Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB. CMFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 CMFB 0 1 Description To clear CMFB, the CPU must read CMFB after it has been set to 1, then write a 0 in this bit This bit is set to 1 when TCNT = TCORB (Initial value) Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA. CMFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 CMFA 0 1 Description To clear CMFA, the CPU must read CMFA after it has been set to 1, then write a 0 in this bit This bit is set to 1 when TCNT = TCORA (Initial value) Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit This bit is set to 1 when TCNT changes from H'FF to H'00 (Initial value) Bit 4--PWM Mode Enable (PWME): This bit sets the timer output to PWM mode. Bit 4 PWME 0 1 Description Normal timer mode PWM mode (Initial value) 169 In PWM mode, bits CCLR1 and CCLR0 and bits OS3 to OS0 must be set so that the contents of TCORA determine the timer output period and the contents of TCORB determine the timer output duty cycle. The timer output pulse period, pulse width, and duty cycle are given by the following equations. If TCORA < TCORB, the output is saturated at a100% duty cycle. (When TCORB TCORA) Timer output pulse period = Selected internal clock period x (TCORA + 1) Timer output pulse width = Selected internal clock period x TCORB Timer output duty cycle = TCORB/(TCORA + 1) TCR PWM Output Mode Direct output (when the above timer pulse width is high) Inverted output (when the above timer pulse width is low) CCLR1 0 0 CCLR0 1 1 OS3 0 1 OS2 1 0 TCSR OS1 1 0 OS0 0 1 In PWM mode, a buffer register is inserted between TCORB and the module data bus, and the data written to TCORB is held in the buffer register until a TCORA compare-match occurs. This makes it easy to achieve PWM output with an undisturbed waveform. With the timer output specification made by bits OS3 to OS0, the priority of a change due to compare-match B is higher. Caution is required since the operation differs from that in normal timer mode. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. In normal timer mode, if compare-match A and B occur simultaneously, any conflict is resolved by giving highest priority to toggle, second-highest priority to 1 output, and third-highest priority to 0 output, as explained in item 9.6.4 in section 9.6, Application Notes. After a reset, the timer output is 0 until the first compare-match event. When all four output select bits (bits OS3 to OS0) are cleared to 0 the timer output signal is disabled. 170 Bit 3 OS3 0 0 1 1 Bit 2 OS2 0 1 0 1 Description No change when compare-match B occurs Output changes to 0 when compare-match B occurs Output changes to 1 when compare-match B occurs Output inverts (toggles) when compare-match B occurs (Initial value) Bit 1 OS1 0 0 1 1 Bit 0 OS0 0 1 0 1 Description No change when compare-match A occurs Output changes to 0 when compare-match A occurs Output changes to 1 when compare-match A occurs Output inverts (toggles) when compare-match A occurs (Initial value) 9.2.5 Bit Serial/Timer Control Register (STCR) 7 (IICS) 0 R/W 6 (IICX1) 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 ICKS0 0 R/W (IICX0) (SYNCE) (PWCKE) (PWCKS) ICKS1 Initial value Read/Write STCR is an 8-bit readable/writable register that selects the TCNT input clock source for the 8-bit timer. STCR is initialized to H'00 by a reset. Bits 7 to 5--I2C Control (IICS, IICX1, IICX0): Reserved. Do not set these bits to 1. Bit 4--Timer Connection Output Enable (SYNCE): Reserved. Do not set this bit to 1. Bits 3 and 2--PWM Timer Control (PWCKE, PWCKS): Reserved. Do not set these bits to 1. Bits 1 and 0--Internal Clock Select 1 and 0 (ICKS1 and ICKS0): These bits, together with bits CKS2 to CKS0 in TCR of the 8-bit timers, select the internal clock to be input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9.2.3, Timer Control Register. 171 9.3 9.3.1 Operation TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the clock source selected by bits CKS2 to CKS0 of the TCR. Internal Clock: Internal clock sources are created from the system clock by a prescaler. The counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 9-2. Bits CKS2 to CKS0 of the TCR can select one of six, or one of three, internal clocks. o Internal clock source TCNT clock pulse TCNT N-1 N N+1 Figure 9-2 Count Timing for Internal Clock Input 172 External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. Figure 9-3 shows incrementation on both edges of the external clock signal. The external clock pulse width must be at least 1.5 system clock periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. o External clock source (TMCI) TCNT clock pulse TCNT N-1 N N+1 Figure 9-3 Count Timing for External Clock Input 173 9.3.2 Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCNT or TCOR. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 9-4 shows the timing of the setting of the compare-match flags. o TCNT N N+1 TCOR N Internal comparematch signal CMF Figure 9-4 Setting of Compare-Match Flags (2) Output Timing (Normal Timer Mode): When a compare-match event occurs, the timer output (TMO0 or TMO1) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. If compare-match A and B occur simultaneously, the higher priority compare-match determines the output level. See item 9.6.4 in section 9.6, Application Notes, for details. 174 Figure 9-5 shows the timing when the output is set to toggle on compare-match A. o Internal comparematch A signal Timer output (TMO) Figure 9-5 Timing of Timer Output (3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 9-6 shows the timing of this operation. o Internal comparematch signal TCNT N H'00 Figure 9-6 Timing of Compare-Match Clear 175 9.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 9-7 shows the timing of this operation. The timer reset pulse width must be at least 1.5 system clock periods. o External reset input (TMRI) Internal clear pulse TCNT N-1 N H'00 Figure 9-7 Timing of External Reset 9.3.4 Setting of TCSR Overflow Flag (1) Setting of TCSR Overflow Flag (OVF): The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 9-8 shows the timing of this operation. o TCNT H'FF H'00 Internal overflow signal OVF Figure 9-8 Setting of Overflow Flag 176 9.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 9-3 lists information about these interrupts. Table 9-3 Interrupt CMIA CMIB OVI 8-Bit Timer Interrupts Description Requested when CMFA and CMIEA are set Requested when CMFB and CMIEB are set Requested when OVF and OVIE are set Low Priority High 9.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. The control bits are set as follows: 1. In the TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. In the TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on comparematch A and to 0 on compare-match B. 2. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Clear counter TMO pin Figure 9-9 Example of Pulse Output 177 9.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. 9.6.1 Contention between TCNT Write and Clear If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 9-10 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus Internal write signal TCNT address Counter clear signal TCNT N H'00 Figure 9-10 TCNT Write-Clear Contention 178 9.6.2 Contention between TCNT Write and Increment If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 9-11 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TNCT N M Write data Figure 9-11 TCNT Write-Increment Contention 179 9.6.3 Contention between TCOR Write and Compare-Match If a compare-match occurs during the T3 state of a write cycle to TCOR, the write takes precedence and the compare-match signal is inhibited. Figure 9-12 shows this type of contention (in normal timer mode). Write cycle: CPU writes to TCOR T1 T2 T3 o Internal address bus TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match A or B signal Inhibited Figure 9-12 Contention between TCOR Write and Compare-Match 180 9.6.4 Contention between Compare-Match A and Compare-Match B If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 9-4 (this applies to normal timer mode). Table 9-4 Priority of Timer Output Output Selection Toggle 1 output 0 output No change Low Priority High 9.6.5 Incrementation Caused by Changing of Internal Clock Source When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 9-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 9-5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. 181 Table 9-5 No. 1 Effect of Changing Internal Clock Sources Timing Description Low low*1 Old clock source New clock source TCNT clock pulse TCNT N CKS rewrite N+1 2 Low high *2 Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite 182 Table 9-5 No. 3 Effect of Changing Internal Clock Sources (cont) Timing chart Old clock source Description High low*3 New clock source *4 TCNT clock pulse TCNT N N+1 CKS rewrite N+2 4 High high Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Notes: 1. 2. 3. 4. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to low. Including a transition from the stopped state to high. Including a transition from high to the stopped state. The switching of clock sources is regarded as a falling edge that increments TCNT. 183 184 Section 10 Watchdog Timer 10.1 Overview The H8/3502 has an on-chip watchdog timer (WDT) that can monitor system operation by resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count to overflow. When this watchdog function is not needed, the watchdog timer module can be used as an interval timer. In interval timer mode, it requests an OVF interrupt at each counter overflow. 10.1.1 Features * Selection of eight clock sources * Selection of two modes: -- Watchdog timer mode -- Interval timer mode * Counter overflow generates an interrupt request or reset: -- Reset or NMI request in watchdog timer mode -- OVF interrupt request in interval timer mode 185 10.1.2 Block Diagram Figure 10-1 is a block diagram of the watchdog timer. Internal NMI (Watchdog timer mode) Interrupt signals OVF (Interval timer mode) Interrupt control Overflow Internal data bus Read/write control TCSR Internal clock source Clock Clock select oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 TCNT TCNT: Timer counter TCSR: Timer control/status register Figure 10-1 Block Diagram of Watchdog Timer 10.1.3 Register Configuration Table 10-1 lists information on the watchdog timer registers. Table 10-1 Register Configuration Addresses Name Timer control/status register Timer counter Abbreviation TCSR TCNT R/W R/(W)* R/W Initial Value H'10 H'00 Write H'FFAA H'FFAA Read H'FFAA H'FFAB Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write 1. 186 10.2 10.2.1 Bit Register Descriptions Timer Counter (TCNT) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCSR is set to 1. TCNT is initialized to H'00 at a reset and when the TME bit is cleared to 0. Note: TCNT is more difficult to write to than other registers. See section 10.2.3, Register Access, for details. 10.2.2 Bit Initial value Read/Write Timer Control/Status Register (TCSR) 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. TCSR is more difficult to write to than other registers. See section 12.2.3, Register Access, for details. TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and performs other functions. (TCSR is write-protected by a password. See section 10.2.3, Register Access, for details.) Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are initialized to 0 by a reset, but retain their values in the standby modes. 187 Bit 7--Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed. Bit 7 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit Set to 1 when TCNT changes from H'FF to H'00 (Initial value) Bit 6--Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or interval timer mode. In interval timer mode, an OVF interrupt request is sent to the CPU when TCNT overflows. In watchdog timer mode, a reset or NMI interrupt is requested. Bit 6 WT/IT 0 1 Description Interval timer mode (OVF request) Watchdog timer mode (reset or NMI request) (Initial value) Bit 5--Timer Enable (TME): Enables or disables the timer. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and stopped TCNT runs and requests a reset or an interrupt when it overflows (Initial value) Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at watchdog timer overflow. Bit 3 RST/NMI 0 1 Description NMI function enabled Reset function enabled (Initial value) 188 Bits 2--0: Clock Select (CKS2-CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this interval. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Clock Source oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 Overflow Interval (oP = 10 MHz) 51.2 s 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms (Initial value) 10.2.3 Register Access The watchdog timer's TCNT and TCSR registers are more difficult to write than other registers. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be used for write access. The TCNT and TCSR registers have the same write address. The write data must be contained in the lower byte of a word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 10-2. The result of the access depicted in figure 10-2 is to transfer the write data from the lower byte to TCNT or TCSR. Writing to TCNT H'FFA8 15 H'5A 87 Write data 0 Writing to TCSR H'FFA8 15 H'A5 87 Write data 0 Figure 10-2 Writing to TCNT and TCSR 189 Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as indicated in table 10-2. These two registers are read like other registers. Byte access instructions can be used. Table 10-2 Read Addresses of TCNT and TCSR Read Address H'FFA8 H'FFA9 Register TCSR TCNT 10.3 10.3.1 Operation Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the entire chip is reset for 518 system clocks (518 o), or an NMI interrupt is requested. Figure 10-3 shows the operation. NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin. Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin NMI. A reset from the watchdog timer has the same vector as an external reset from the RES pin. The reset source can be determined by the XRST bit in SYSCR. WDT overflow H'FF TCNT count WT/IT = 1 TME = 1 H'00 OVF = 1 WT/IT = 1 TME = 1 H'00 written to TCNT H'00 written to TCNT Time t Reset 518 o Figure 10-3 Operation in Watchdog Timer Mode 190 10.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In interval timer mode, an OVF request is generated each time the timer count overflows. This function can be used to generate OVF requests at regular intervals. See figure 10-4. H'FF TCNT count Time t H'00 WT/IT = 0 TME = 1 OVF request OVF request OVF request OVF request OVF request Figure 10-4 Operation in Interval Timer Mode 10.3.3 Setting the Overflow Flag The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 10-5. o TCNT Internal overflow signal H'FF H'00 OVF Figure 10-5 Setting the OVF Bit 191 10.4 10.4.1 Application Notes Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 10-6. Write cycle (CPU writes to TCNT) T1 o T2 T3 Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Counter write data Figure 10-6 TCNT Write-Increment Contention 10.4.2 Changing the Clock Select Bits (CKS2 to CKS0) Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. 10.4.3 Recovery from Software Standby Mode TCSR bits, except bits 0-2, and the TCNT counter are reset when the chip recovers from software standby mode. Re-initialize the watchdog timer as necessary to resume normal operation. 192 Section 11 Serial Communication Interface 11.1 Overview The H8/3502 includes two serial communication interface channels (SCI0 and SCI1) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 11.1.1 Features The features of the on-chip serial communication interface are: * Asynchronous mode The H8/3502 can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. It also has a multiprocessor communication function for communication with other processors. Twelve data formats are available. -- -- -- -- -- -- Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Error detection: Parity, overrun, and framing errors Break detection: When a framing error occurs, the break condition can be detected by reading the level of the RxD line directly. * Synchronous mode The SCI can communicate with chips able to perform clocked synchronous data transfer. -- Data length: 8 bits -- Error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. * Built-in bit rate generator Any specified bit rate can be generated. 193 * Internal or external clock source The SCI can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the SCK0 or SCK1 pin. * Four interrupts TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently. 194 11.1.2 Block Diagram Figure 11-1 shows a block diagram of one serial communication interface channel. Bus interface BRR Baud rate generator Clock Internal data bus Module data bus RDR TDR SSR SCR SMR RxD RSR TSR Communication control Parity generate Parity check TxD Internal o oP/4 clock oP/16 oP/64 SCK External clock source TEI TXI RXI ERI Interrupt signals RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Receive shift register (8 bits) Receive data register (8 bits) Transmit shift register (8 bits) Transmit data register (8 bits) Serial mode register (8 bits) Serial control register (8 bits) Serial status register (8 bits) Bit rate register (8 bits) Figure 11-1 Block Diagram of Serial Communication Interface 195 11.1.3 Input and Output Pins Table 11-1 lists the input and output pins used by the SCI module. Table 11-1 SCI Input/Output Pins Channel 0 Name Serial clock input/output Receive data input Transmit data output 1 Serial clock input/output Receive data input Transmit data output Abbr. SCK 0 RxD0 TxD0 SCK 1 RxD1 TxD1 I/O Input/output Input Output Input/output Input Output Function Serial clock input and output Receive data input Transmit data output Serial clock input and output Receive data input Transmit data output Note: In this manual, the channel subscript has been deleted, and only SCK, RxD, and TxD are used. 196 11.1.4 Register Configuration Table 11-2 lists the SCI registers. These registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. Table 11-2 SCI Registers Channel 0 Name Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial communication mode register 1 Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Abbr. RSR RDR TSR TDR SMR SCR SSR BRR SCMR RSR RDR TSR TDR SMR SCR SSR BRR R/W -- R -- R/W R/W R/W R/(W)* R/W R/W -- R -- R/W R/W R/W R/(W)* R/W Value -- H'00 -- H'FF H'00 H'00 H'84 H'FF H'F2 -- H'00 -- H'FF H'00 H'00 H'84 H'FF Address -- H'FFDD -- H'FFDB H'FFD8 H'FFDA H'FFDC H'FFD9 H'FFDE -- H'FFE5 -- H'FFE3 H'FFE0 H'FFE2 H'FFE4 H'FFE1 Note: * Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits. 197 11.2 11.2.1 Bit Register Descriptions Receive Shift Register (RSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Read/Write RSR is a shift register that converts incoming serial data to parallel data. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write RSR directly. 11.2.2 Bit Initial value Read/Write Receive Data Register (RDR) 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R RDR stores received data. As each character is received, it is transferred from RSR to RDR, enabling RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes. 11.2.3 Bit Read/Write Transmit Shift Register (TSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a shift register that converts parallel data to serial transmit data. When transmission of one character is completed, the next character is moved from the transmit data register (TDR) to TSR and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is transferred to TSR. The CPU cannot read or write TSR directly. 198 11.2.4 Bit Transmit Data Register (TDR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value Read/Write TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is possible by writing the next data in TDR while the current data is being transmitted from TSR. TDR is initialized to H'FF by a reset and in the standby modes. 11.2.5 Bit Initial value Read/Write Serial Mode Register (SMR) 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SMR is an 8-bit readable/writable register that controls the communication format and selects the clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the standby modes. For further information on the SMR settings and communication formats, see tables 11-5 and 11-7 in section 11.3, Operation. Bit 7--Communication Mode (C/A): This bit selects asynchronous or synchronous communication mode. Bit 7 C/A 0 1 Description Asynchronous communication Synchronous communication (Initial value) 199 Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. Bit 6 CHR 0 1 Description 8 bits per character 7 bits per character (Bits 6 to 0 of TDR and RDR are used for transmitting and receiving, respectively) (Initial value) Bit 5--Parity Enable (PE): This bit selects whether to add and check for a parity bit in asynchronous mode. It is ignored in synchronous mode, and when a multiprocessor format is used. Bit 5 PE 0 Description Transmit: No parity bit is added Receive: Parity is not checked 1 Transmit: A parity bit is added Receive: Parity is checked (Initial value) Bit 4--Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in synchronous mode. Bit 4 O/E 0 1 Description Even parity Odd parity (Initial value) 200 Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in synchronous mode, and when a multiprocessor format is used. Bit 3 STOP 0 Description One stop bit Transmit: One stop bit is added Receive: One stop bit is checked to detect framing errors Two stop bits Transmit: Two stop bits are added Receive: The first stop bit is checked to detect framing errors If the second stop bit is a space (0), it is regarded as the next start bit. (Initial value) 1 Bit 2--Multiprocessor Mode (MP): This bit selects the multiprocessor format. When multiprocessor format is selected, the parity settings of the parity enable bit (PE) and parity mode bit (O/E) are ignored. The MP bit is valid only in asynchronous mode, and is ignored in synchronous mode. Bit 2 MP 0 1 Description Multiprocessor communication function is disabled Multiprocessor communication function is enabled (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the on-chip baud rate generator. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description o clock oP/4 clock oP/16 clock oP/64 clock (Initial value) 201 11.2.6 Bit Serial Control Register (SCR) 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value Read/Write SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 by a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1. Bit 7 TIE 0 1 Description The TDR-empty interrupt request (TXI) is disabled The TDR-empty interrupt request (TXI) is enabled (Initial value) Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1. Bit 6 RIE 0 1 Description The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are disabled The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are enabled (Initial value) Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a general-purpose I/O port. Bit 5 TE 0 1 Description The transmit function is disabled The TxD pin can be used for general-purpose I/O The transmit function is enabled The TxD pin is used for output (Initial value) 202 Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as a general-purpose I/O port. Bit 4 RE 0 1 Description The receive function is disabled The RxD pin can be used for general-purpose I/O The receive function is enabled The RxD pin is used for input (Initial value) Bit 3--Multiprocessor Interrupt Enable (MPIE): When serial data is received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receiveerror interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or disables the transfer of receive data from RSR to RDR, and enables or disables setting of the RDRF, FER, PER, and ORER bits in the serial status register (SSR). The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode. Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition data is received regardless of the value of the multiprocessor bit in the receive data. Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is 1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and receive-error interrupts are enabled. Bit 3 MPIE 0 1 Description The multiprocessor receive interrupt function is disabled (Normal receive operation) (Initial value) The multiprocessor receive interrupt function is enabled. During the interval before data with the multiprocessor bit set to 1 is received, the receive interrupt request (RXI) and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in the serial status register (SSR), and no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the following times: (1) When 0 is written in MPIE (2) When data with the multiprocessor bit set to 1 is received 203 Bit 2--Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to 1. Bit 2 TEIE 0 1 Description The TSR-empty interrupt request (TEI) is disabled The TSR-empty interrupt request (TEI) is enabled (Initial value) Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal. Bit 1 CKE1 0 Description Internal clock source When C/A = 1, the serial clock signal is output at the SCK pin When C/A = 0, output depends on the CKE0 bit External clock source The SCK pin is used for input (Initial value) 1 Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when synchronous mode is selected. For further information on the communication format and clock source selection, see table 11-6 in section 11.3, Operation. Bit 0 CKE0 0 1 Description The SCK pin is not used by the SCI (and is available as a general-purpose I/O port) The SCK pin is used for serial clock output (Initial value) 204 11.2.7 Bit Serial Status Register (SSR) 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value Read/Write Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely be written in TDR. Bit 7 TDRE 0 1 Description To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in this bit This bit is set to 1 at the following times: (1) When TDR contents are transferred to TSR (2) When the TE bit in SCR is cleared to 0 (Initial value) Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to the RDR. Bit 6 RDRF 0 1 Description To clear RDRF, the CPU must read RDRF after it has been set to 1, then write a 0 in this bit This bit is set to 1 when one character is received without error and transferred from RSR to RDR (Initial value) 205 Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER 0 1 Description To clear ORER, the CPU must read ORER after it has been set to 1, then write a 0 in this bit This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1) (Initial value) Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in asynchronous mode. It has no meaning in synchronous mode. Bit 4 FER 0 1 Description To clear FER, the CPU must read FER after it has been set to 1, then write a 0 in this bit This bit is set to 1 if a framing error occurs (stop bit = 0) (Initial value) Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in synchronous mode, or when a communication format without parity bits is used. Bit 3 PER 0 1 Description To clear PER, the CPU must read PER after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in SMR) 206 Bit 2--Transmit End (TEND): This bit indicates that the serial communication interface has stopped transmitting because there was no valid data in TDR when the last bit of the current character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control register (SCR) is cleared to 0. The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first start transmitting data, which clears TEND to 0, then set TEIE to 1. Bit 2 TEND 0 1 Description To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then write a 0 in TDRE This bit is set to 1 when: (1) TE = 0 (2) TDRE = 1 at the end of transmission of a character (Initial value) Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. This bit retains its previous value in synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0 even if a multiprocessor format is used. MPB can be read but not written. Bit 1 MPB 0 1 Description Multiprocessor bit = 0 in receive data Multiprocessor bit = 1 in receive data (Initial value) Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. The MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in synchronous mode, or when a multiprocessor format is not used. Bit 0 MPBT 0 1 Description Multiprocessor bit = 0 in transmit data Multiprocessor bit = 1 in transmit data (Initial value) 207 11.2.8 Bit Bit Rate Register (BRR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value Read/Write BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit rate output by the baud rate generator. BRR is initialized to H'FF by a reset and in the standby modes. Tables 11-3 and 11-4 show examples of BRR settings. Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) o Frequency (MHz) 2 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 0 0 -- N 52 155 77 155 77 38 19 9 4 2 -- 3 Error (%) +0.50 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- 208 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 3.6864 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 6 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0 0 0 +0.16 +0.16 +0.16 -2.34 -2.34 0 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 4 5 4 6.144 Error (%) +0.08 0 0 0 0 0 0 0 0 +2.40 0 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0 0 0 0 0 0 0 0 -- 0 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 -- 209 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 9.8304 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0 0 0 0 0 0 0 0 -1.70 0 n 3 2 2 1 1 0 0 0 0 0 0 N 43 129 64 129 64 129 64 32 15 9 7 10 Error (%) +0.88 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 0 +1.73 Note: If possible, the error should be within 1%. In the shaded section, if oP = o/2, the bit rate is cut in half. In this case, BRR settings for the desired bit rate should be referenced from the column of one-half the actual system clock frequency (o). B = F x 10 6/[64 x 2 2n-1 x (N + 1)] N = F x 10 6/[64 x 2 2n-1 x B] - 1 B: Bit rate (bits/second) N: BRR value (0 N 255) F: oP (MHz) when n 0, or o (MHz) when n = 0 n: Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o oP/4 oP/16 oP/64 Bit rate error can be calculated with the formula below. Error (%) = F x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1 210 Table 11-4 Examples of BRR Settings in Synchronous Mode (When oP = o) o Frequency (MHz) 2 Bit Rate 100 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 4M Notes: In the shaded section, if o P = o/2, the bit rate is cut in half. In this case, BRR settings for the desired bit rate should be referenced from the column of one-half the actual system clock frequency (o). Blank: No setting is available. --: A setting is available, but the bit rate is inaccurate. *: Continuous transfer is not possible. B = F x 10 6/[8 x 2 2n-1 x (N + 1)] N = F x 10 6/[8 x 2 2n-1 x B] - 1 B: Bit rate (bits per second) N: BRR value (0 N 255) F: oP (MHz) when n 0, or o (MHz) when n = 0 n: Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o oP/4 oP/16 oP/64 n -- 2 1 1 0 0 0 0 0 0 0 0 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 5 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0* 211 11.2.9 Bit Serial Communication Mode Register (SCMR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value Read/Write SCMR is an 8-bit readable/writable register that selects the function of SCI0. SCMR is initialized to H'F2 by a reset and in the standby modes. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--Data Transfer Direction (SDIR): This bit selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2--Data Invert (SINV): This bit specifies inversion of the data logic level. Inversion specified by the SINV bit applies only to data bits D7 to D0. In order to invert the parity bit, the O/E bit in SMR must be inverted. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are TDR contents are stored in RDR as they are TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form (Initial value) Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--Serial Communication Mode Select (SMIF): This bit is reserved. A 1 must not be written to this bit. Bit 0 SMIF 0 1 Description Normal SCI mode Reserved mode (Initial value) 212 11.3 11.3.1 Operation Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on SMR settings as indicated in table 11-5. The clock source depends on the settings of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR as indicated in table 11-6. Asynchronous Mode * Data length: 7 or 8 bits can be selected. * A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be selected. (These selections determine the communication format and character length.) * Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in receive data, and the line-break condition can be detected. * SCI clock source: an internal or external clock source can be selected. -- Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. -- External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * Communication format: The data length is 8 bits. * Overrun errors (ORER) can be detected in receive data. * SCI clock source: an internal or external clock source can be selected. -- Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock signal to external devices. -- External clock: The on-chip baud rate generator is not used. The SCI operates on the input serial clock. 213 Table 11-5 Communication Formats Used by SCI SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- 0 1 1 0 1 1 -- -- -- -- Synchronous mode 8 bits None Asynchronous mode (multiprocessor format) 8 bits Present None Present 7 bits None Data Length 8 bits Communication Format Multiprocessor Bit None Parity Bit None StopBit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7 bits 1 bit 2 bits None Mode Asynchronous mode Table 11-6 SCI Clock Source Selection SMR Bit 7 C/A 0 Bit 1 CKE1 0 SCR Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 External Serial clock input Sync Internal Serial clock output External Mode Async Serial Transmit/Receive Clock Clock Source Internal SCK Pin Function Input/output port (not used by SCI) Serial clock output at bit rate Serial clock input at 16 x bit rate 214 11.3.2 Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 11-2 shows the general format of one character sent or received in asynchronous mode. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). Start bit D0 D1 Dn Parity Stop bit Idle state (mark) 1 bit 7 or 8 bits 0 or 1 bit 1 or 2 bits One unit of data (one character or frame) Figure 11-2 Data Format in Asynchronous Mode (Example of 8-Bit Data with Parity Bit and Two Stop Bits) 215 (1) Data Format: Table 11-7 lists the data formats that can be sent and received in asynchronous mode. Twelve formats can be selected by bits in the serial mode register (SMR). Table 11-7 Data Formats in Asynchronous Mode SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data Notes: SMR: S: STOP: P: MPB: Serial mode register Start bit Stop bit Parity bit Multiprocessor bit (2) Clock: In asynchronous mode it is possible to select either an internal clock created by the onchip baud rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR). Refer to table 11-6. If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. Figure 11-3 shows the phase relationship between the output clock and transmit data. 216 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 11-3 Phase Relationship between Clock Output and Transmit Data (Asynchronous Mode) (3) Transmitting and Receiving Data SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI following the procedure in figure 11-4. Note: When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. 217 Initialization 1. Clear TE and RE bits to 0 in SCR 2. 1 Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) Select the clock source in the serial control register (SCR). Leave TE and RE cleared to 0. If clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in SCR. Select the communication format in the serial mode register (SMR). Write the value corresponding to the bit rate in the bit rate register (BRR). This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR). Setting TE or RE enables the SCI to use the TxD or RxD pin. Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable interrupts. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 3. 2 Select communication format in SMR 4. 3 Set value in BRR 1 bit interval elapsed? Yes 4 No Set TE or RE to 1 in SCR, and set RIE, TIE, TEIE, and MPIE as necessary Start transmitting or receiving Figure 11-4 Sample Flowchart for SCI Initialization 218 Transmitting Serial Data: Follow the procedure in figure 11-5 for transmitting serial data. 1 Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. If a multiprocessor format is selected, after writing the transmit data write 0 or 1 in the multiprocessor bit transfer (MPBT) in SSR. Transition of the TDRE bit from 0 to 1 can be reported by an interrupt. Start transmitting 2. 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR If using multiprocessor format, select MPBT value in SSR Clear TDRE bit to 0 Serial transmission End of transmission? Yes No 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear TE to 0 in SCR. 3 Read TEND bit in SSR No TEND = 1? Yes Output break signal? Yes Set DR = 0, DDR = 1 Clear TE bit in SCR to 0 4 No End Figure 11-5 Sample Flowchart for Transmitting Serial Data 219 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. b. c. Start bit: One 0 bit is output. Transmit data: Seven or eight bits are output, LSB-first. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. Stop bit: One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. 2. d. e. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt). 220 Figure 11-6 shows an example of SCI transmit operation in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark) TDRE TEND TXI TXI interrupt handler request writes data in TDR and clears TDRE to 0 1 frame TXI request TEI request Figure 11-6 Example of SCI Transmit Operation (8-Bit Data with Parity and One Stop Bit) 221 Receiving Serial Data: Follow the procedure in figure 11-7 for receiving serial data. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. To continue receiving serial data: read RDR and clear RDRF to 0 before the stop bit of the current frame is received. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER bits in SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Transmitting and receiving cannot resume if ORER, PER, or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Start receiving 2. Read ORER, PER, and FER in SSR 3. PER RER ORER = 1? No 2 Read RDRF bit in SSR Yes 4 Error handling No 4. RDRF = 1? Yes 3 Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? Yes Clear RE to 0 in SCR No End Start error handling FER = 1? No Discriminate and process error, and clear flags Return Yes Break? No Yes Clear RE to 0 in SCR End Figure 11-7 Sample Flowchart for Receiving Serial Data 222 In receiving, the SCI operates as follows. 1. 2. 3. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. Receive data is shifted into RSR in order from LSB to MSB. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. b. c. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 11-8. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error) interrupt. 223 Figure 11-8 shows an example of SCI receive operation in asynchronous mode. Table 11-8 Receive Error Conditions and SCI Operation Receive error Overrun error Abbreviation ORER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR Framing error Parity error FER PER 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 Idle state (mark) RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0 Framing error, ERI request Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 224 (4) Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID matching the received data continues to receive further incoming data. Multiple processors can send and receive data in this way. Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11-7. 225 Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: multiprocessor bit Figure 11-9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) 226 Transmitting Multiprocessor Serial Data: See figures 11-5 and 11-6. Receiving Multiprocessor Serial Data: Follow the procedure in figure 11-10 for receiving multiprocessor serial data. 1 Initialize Start receiving 1. SCI initialization: the receive data function of the RxD pin is selected automatically. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. SCI status check and ID check: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and compare with the processor's own ID. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR) and write 0 in the RDRF bit. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume while ORER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 2. 2 Set MPIE bit to 1 in SCR Read ORER and FER bits in SSR FER ORER = 1? No 3. Yes 4. 3 Read RDRF bit in SSR No RDRF = 1? Yes Read receive data from RDR No 5. Own ID? Yes Read ORER and FER bits in SSR FER + ORER = 1? No 4 Read RDRF bit in SSR Yes 5 Error handling RDRF = 1? Yes No Start error handling Read receive data from RDR FER = 1? Finished receiving? Yes Clear RE to 0 in SCR End No No Discriminate and process error, and clear flags Return Yes Break? No Yes Clear RE bit to 0 in SCR End Figure 11-10 Sample Flowchart for Receiving Multiprocessor Serial Data 227 Figure 11-11 shows an example of an SCI receive operation using a multiprocessor format (8-bit data with multiprocessor bit and one stop bit). 1 Start bit 0 D0 Data (ID1) D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data1) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark) MPIE RDRF RDR value MPB detection MPIE = 0 RXI request RXI handler reads RDR data and clears RDRF to 0 ID1 Not own ID, so MPIE is set to 1 again No RXI request, RDR not updated (Multiprocessor interrupt) (a) Own ID does not match data 1 Start bit 0 D0 Data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark) MPIE RDRF RDR value ID1 MPB detection MPIE = 0 RXI request RXI handler reads RDR data and clears RDRF to 0 ID2 Own ID, so receiving continues, with data received at each RXI Data 2 MPIE set to 1 again (Multiprocessor interrupt) (b) Own ID matches data Figure 11-11 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 228 11.3.3 Synchronous Mode (1) Overview: In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 11-12 shows the general format in synchronous serial communication. One unit (character or frame) of serial data * Serial clock LSB Serial data Don't care Note: * High except in continuous transmitting or receiving Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 11-12 Data Format in Synchronous Communication In synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. Data is received in synchronization with the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register (SCR). See table 11-6. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains at the high level. 229 (2) Transmitting and Receiving Data SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See figure 11-4. When switching from asynchronous mode to synchronous mode, check that the ORER, FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER, FER, or PER is set to 1. Transmitting Serial Data: Follow the procedure in figure 11-13 for transmitting serial data. 1 Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. Start transmitting 2. 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR Serial transmission End of transmission? Yes No 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 3 Read TEND bit in SSR No TEND = 1? Yes Clear TE bit to 0 in SCR End Figure 11-13 Sample Flowchart for Serial Transmitting 230 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSRempty interrupt) is requested at this time. After the end of serial transmission, the SCK pin is held at the high level. 2. 4. 231 Figure 11-14 shows an example of SCI transmit operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt TXI handler writes request data in TDR and clears TDRE to 0 1 frame TEI request Figure 11-14 Example of SCI Transmit Operation 232 Receiving Serial Data: Follow the procedure in figure 11-15 for receiving serial data. When switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and receiving will be disabled. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. To continue receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. When clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. When preparations to receive the next data are completed, clear the ORER bit to 0. This causes receiving to resume, so return to the step marked 2 in the flowchart. Start receiving 2. Read ORER in SSR ORER = 1? No 2 Read RDRF bit in SSR Yes 4 Error handling 3. 4. No RDRF = 1? Yes 3 Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? Yes Clear RE to 0 in SCR No End Start error handling Overrun error handling Clear ORER to 0 in SSR Return Figure 11-15 Sample Flowchart for Serial Receiving 233 In receiving, the SCI operates as follows. 1. If an external clock is selected, data is input in synchronization with the input clock. If clock output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the serial clock and input of data resume as soon as the ORER bit is cleared to 0. Receive data is shifted into RSR in order from LSB to MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 11-8. Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR is set to 1, the SCI requests an ERI (receive-error) interrupt. When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. 2. 234 Figure 11-16 shows an example of SCI receive operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF to 0 1 frame RXI request Overrun error, ERI request Figure 11-16 Example of SCI Receive Operation 235 Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure 11-17 for transmitting and receiving serial data simultaneously. If clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. 1 Initialize 1. Start 2. 2 Read TDRE bit in SSR SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. SCI status check and receive data read: read the serial status register (SSR), check that the RDRF bit is 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. To continue transmitting and receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit and check that it is set to 1, indicating that it is safe to write; then write data in TDR and clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. No TDRE = 1? 3. Yes 3 Write transmit data in TDR and clear TDRE bit to 0 in SSR 4. Read ORER bit in SSR ORER = 1? No Read RDRF bit in SSR Yes 5 Error handling 5. No RDRF = 1? Yes 4 Read receive data from RDR and clear RDRF bit to 0 in SSR End of transmitting and receiving? Yes Clear TE and RE bits to 0 in SCR No End Figure 11-17 Sample Flowchart for Serial Transmitting and Receiving Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1. 236 11.4 Interrupts The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 11-9 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error. The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates that the SCI has stopped transmitting data. Table 11-9 SCI Interrupt Sources Interrupt ERI RXI TXI TEI Description Receive-error interrupt (ORER, FER, or PER) Receive-end interrupt (RDRF) TDR-empty interrupt (TDRE) TSR-empty interrupt (TEND) Low Priority High 11.5 Application Notes Application programmers should note the following features of the SCI. (1) TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before writing to TDR. (2) Multiple Receive Errors: Table 11-10 lists the values of flag bits in SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to RDR. 237 Table 11-10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur SSR Bits Receive error Overrun error Framing error Parity error Overrun and framing errors Overrun and parity errors Framing and parity errors RDRF 1*1 0 0 1*1 1*1 0 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 RSR RDR*2 No Yes Yes No No Yes No Overrun, framing, and parity errors1*1 Notes: 1. 2. Set to 1 before the overrun error occurs. Yes: The RSR contents are transferred to RDR. No: The RSR contents are not transferred to RDR. (3) Line Break Detection: When the RxD pin receives a continuous stream of 0's in asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from RSR to RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. (4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 11-18. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%. 238 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 1 2 3 4 5 Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1 Sync sampling Data sampling Figure 11-18 Sampling Timing (Asynchronous Mode) M = {[0.5 - 1/(2N)] - (D - 0.5)/N - (L - 0.5)F} x 100 [%] (1) M: Receive margin N: Ratio of basic clock to bit rate (N=16) D: Duty factor of clock--ratio of high pulse width to low width (0.5 to 1.0) L: Frame length (9 to 12) F: Absolute clock frequency deviation When D = 0.5 and F = 0 M = (0.5 -1/2 x 16) x 100 [%] = 46.875% (2) 239 240 Section 12 Host Interface 12.1 Overview The H8/3502 has an on-chip host interface (HIF) that provides a dual-channel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a master-slave communication system in which the H8/3502 chip is slaved to a host processor. The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via five control signals from the host processor (CS1, CS2, HA0, IOR, and IOW), four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1 and CS2 signals select one of the two interface channels. Note: If one of the two interface channels will not be used, tie the unused CS pin to VCC. For example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS1 to VCC . 241 12.1.1 Block Diagram Figure 12-1 is a block diagram of the host interface. (Internal interrupt signals) IBF2 IBF1 HDB7 to HDB0 CS1 CS2 IOR IOW HA0 Control logic IDR1 ODR1 Host data bus STR1 IDR2 ODR2 STR2 HICR Module data bus Host interrupt request Fast A20 gate control HIRQ1 HIRQ11 HIRQ12 GA20 Port 4 Internal data bus Legend IDR1: Input data register 1 IDR2: Input data register 2 ODR1: Output data register 1 ODR2: Output data register 2 STR1: Status register 1 STR2: Status register 2 HICR: Host interface control register Bus interface Figure 12-1 Host Interface Block Diagram 242 12.1.2 Input and Output Pins Table 12-1 lists the input and output pins of the host interface module. Table 12-1 HIF Input/Output Pins Name I/O read I/O write Chip select 1 Chip select 2 Command/data Abbreviation IOR IOW CS 1 CS 2 HA 0 Port P76 P75 P74 P46 P77 I/O Input Input Input Input Input Function Host interface read signal Host interface write signal Host interface chip select signal for IDR1, ODR1, STR1 Host interface chip select signal for IDR2, ODR2, STR2 Host interface address select signal In host read access, this signal selects the status registers (STR1, STR2) or data registers (ODR1, ODR2). In host write access to the data registers (IDR1, IDR2), this signal indicates whether the host is writing a command or data. Data bus Host interrupt 1 HDB7 to HDB 0 P37 to P3 0 I/O HIRQ1 P44 P43 P45 P47 Output Output Output Output Host interface data bus (single-chip mode) Interrupt output 1 to host Interrupt output 11 to host Interrupt output 12 to host A20 gate control signal output Host interrupt 11 HIRQ11 Host interrupt 12 HIRQ12 Gate A20 GA20 243 12.1.3 Register Configuration Table 12-2 lists the host interface registers. Table 12-2 HIF Registers R/W Name System control register Host interface control register Input data register 1 Output data register 1 Status register 1 Input data register 2 Output data register 2 Status register 2 Serial/timer control register Notes: 1. 2. 3. 4. 5. 6. Abbreviation SYSCR HICR IDR1 ODR1 STR1 IDR2 ODR2 STR2 STCR Slave R/W*1 R/W R R/W Host -- -- W R Initial Value H'09 H'F8 -- -- H'00 -- -- H'00 H'00 Master Address*4 Slave Address*3 CS 1 CS 2 HA0 H'FFC4 H'FFF0 H'FFF4 H'FFF5 H'FFF6 H'FFFC H'FFFD H'FFFE H'FFC3 -- -- 0 0 0 1 1 1 -- -- -- 1 1 1 0 0 0 -- -- -- 0/1 *5 0 1 0 0/1 *5 1 -- R/(W)*2 R R R/W W R R/(W)*2 R R/W -- Bit 3 is a read-only bit. The user-defined bits (bits 7 to 4, 2) are read/write accessible from the slave processor. Address when accessed from the slave processor. Pin inputs used in access from the host processor. The HA 0 input discriminates between writing of commands and data. Registers in slave addresses H'FFF0 to H'FFFF can only be read or written to when the HIE bit in the system control register (SYSCR) is set to 1. 244 12.2 12.2.1 Bit Register Descriptions System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write SYSCR is an 8-bit readable/writable register which controls chip operations. Host interface functions are enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in the hardware standby modes. Bit 1--Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the host interface handles host-slave data transfers, operating in slave mode. Bit 1 HIE 0 1 Description The host interface is disabled The host interface is enabled (slave mode) (Initial value) 12.2.2 Bit Host Interface Control Register (HICR) 7 -- 1 -- -- 6 -- 1 -- -- 5 -- 1 -- -- 4 -- 1 -- -- 3 -- 1 -- -- 2 IBFIE2 0 R/W -- 1 0 R/W -- 0 0 R/W -- IBFIE1 FGA20E Initial value Slave Read/Write Host Read/Write HICR is an 8-bit readable/writable register which controls host interface interrupts and the fast A20 gate function. HICR is initialized to H'F8 by a reset and in the standby modes. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. 245 Bit 2--Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt to the slave CPU. Bit 2 IBFIE2 0 1 Description IDR2 input buffer full interrupt is disabled IDR2 input buffer full interrupt is enabled (Initial value) Bit 1-- Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt to the slave CPU. Bit 1 IBFIE1 0 1 Description IDR1 input buffer full interrupt is disabled IDR1 input buffer full interrupt is enabled (Initial value) Bit 0--Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using software to manipulate the P81 output. Bit 0 FGA20E Description 0 1 Disables fast A20 gate function Enables fast A20 gate function (Initial value) 12.2.3 Bit Input Data Register 1 (IDR1) 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 IDR4 -- R W 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 IDR0 -- R W Initial value Slave Read/Write Host Read/Write IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CS1 is low, information on the host data bus is written into IDR1 at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STR1 to indicate whether the written information is a command or data. The initial values of IDR1 after a reset and in the standby modes are undetermined. 246 12.2.4 Bit Output Data Register 1 (ODR1) 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 ODR4 -- R/W R 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 ODR0 -- R/W R Initial value Slave Read/Write Host Read/Write ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register to the host processor. The ODR1 contents are output on the host data bus when HA0 is low, CS1 is low, and IOR is low. The initial values of ODR1 after a reset and in standby mode are undetermined. 12.2.5 Bit Initial value Slave Read/Write Host Read/Write Status Register 1 (STR1) 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 OBF 0 R R STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR1 is initialized to H'00 by a reset and in the standby modes. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR1, and indicates whether IDR1 contains data or a command. Bit 3 C/D 0 1 Description Contents of IDR1 are data Contents of IDR1 are a command (Initial value) 247 Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR1. Bit 1 IBF 0 1 Description This bit is cleared when the slave processor reads IDR1 This bit is set when the host processor writes to IDR1 (Initial value) Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR1. Bit 0 OBF 0 1 Description This bit is cleared when the host processor reads ODR1 This bit is set when the slave processor writes to ODR1 (Initial value) Table 12-3 shows the conditions for setting and clearing the STR1 flags. Table 12-3 Set/Clear Timing for STR1 Flags Flag C/D IBF OBF Setting Condition Rising edge of host's write signal (IOW) when HA 0 is high Rising edge of host's write signal (IOW) when writing to IDR1 Falling edge of slave's internal write signal (WR) when writing to ODR1 Clearing Condition Rising edge of host's write signal (IOW) when HA 0 is low Falling edge of slave's internal read signal (RD) when reading IDR1 Rising edge of host's read signal (IOR) when reading ODR1 12.2.6 Bit Input Data Register 2 (IDR2) 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 IDR4 -- R W 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 IDR0 -- R W Initial value Slave Read/Write Host Read/Write IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CS2 is low, information on the host data bus is written into IDR2 at the 248 rising edge of IOW. The HA0 state is also latched into the C/D bit in STR2 to indicate whether the written information is a command or data. The initial values of IDR2 after a reset and in the standby modes are undetermined. 12.2.7 Bit Initial value Slave Read/Write Host Read/Write Output Data Register 2 (ODR2) 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 ODR4 -- R/W R 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 ODR0 -- R/W R ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the host processor. The ODR2 contents are output on the host data bus when HA0 is low, CS2 is low, and IOR is low. 12.2.8 Bit Initial value Slave Read/Write Host Read/Write Status Register 2 (STR2) 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 OBF 0 R R STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR2 is initialized to H'00 by a reset and in the standby modes. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR2, and indicates whether IDR2 contains data or a command. Bit 3 C/D 0 1 Description Contents of IDR2 are data Contents of IDR2 are a command (Initial value) 249 Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR2. Bit 1 IBF 0 1 Description This bit is cleared when the slave processor reads IDR2 This bit is set when the host processor writes to IDR2 (Initial value) Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to 0 when the host processor reads ODR2. Bit 0 OBF 0 1 Description This bit is cleared when the host processor reads ODR2 This bit is set when the slave processor writes to ODR2 (Initial value) Table 12-4 shows the conditions for setting and clearing the STR2 flags. Table 12-4 Set/Clear Timing for STR2 Flags Flag C/D IBF OBF Setting Condition Rising edge of host's write signal (IOW) when HA 0 is high Rising edge of host's write signal (IOW) when writing to IDR2 Falling edge of slave's internal write signal (WR) when writing to ODR2 Clearing Condition Rising edge of host's write signal (IOW) when HA 0 is low Falling edge of slave's internal read signal (RD) when reading IDR2 Rising edge of host's read signal (IOR) when reading ODR2 250 12.3 12.3.1 Operation Host Interface Operation The host interface is activated by setting the HIE bit (bit 1) to 1 in SYSCR, establishing slave mode. Activation of the host interface (entry to slave mode) appropriates the related I/O lines in port 3 (data), port 4 or 7 (control) and port 4 (host interrupt requests) for interface use. For host interface read/write timing diagrams, see section 19.3.8, Host Interface Timing. 12.3.2 Control States Table 12-5 indicates the slave operations carried out in response to host interface signals from the host processor. Table 12-5 Host Interface Operation CS 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CS 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IOR 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IOW 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Prohibited Prohibited Data read from output data register 1 (ODR1) Status read from status register 1 (STR1) Data write to input data register 1 (IDR1) Command write to input data register 1 (IDR1) Idle state Idle state Prohibited Prohibited Data read from output data register 2 (ODR2) Status read from status register 2 (STR2) Data write to input data register 2 (IDR2) Command write to input data register 2 (IDR2) Idle state Idle state 251 12.3.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be output under software control, or a fast A20 gate signal can be output under hardware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0). Note: * Intel microprocessor. Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs it at the gate A20 pin (P4 7 /GA20). Fast A20 Gate Operation: When the FGA20E bit is set to 1, P47/GA20 is used for output of a fast A20 gate signal. Bit P47DDR must be set to 1 to assign this pin for output. The initial output from this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is available only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on software or interrupts, and is faster than the regular processing using interrupts. Table 12-6 lists the conditions that set and clear GA20 (P47). Figure 12-2 describes the GA20 output in flowchart form. Table 127 indicates the GA20 output signal values. Table 12-6 GA20 (P47) Set/Clear Timing Pin Name GA20 (P4 7) Setting Condition Clearing Condition Rising edge of the host's write signal Rising edge of the host's write signal (IOW) (IOW) when bit 1 of the written data when bit 1 of the written data is 0 and the data follows an H'D1 host command is 1 and the data follows an H'D1 host command 252 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P47/GA20 Figure 12-2 GA 20 Output 253 Table 12-7 Fast A20 Gate Output Signal HA0 Data/Command 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 H'D1 command "1" data*1 H'FF command H'D1 command "0" data*2 H'FF command H'D1 command "1" data*1 Internal CPU GA20 Interrupt Flag (P47) Remarks 0 0 0 0 0 0 0 0 Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Short turn-off sequence Short turn-on sequence Turn-off sequence Turn-on sequence Command other than H'FF 1 and H'D1 H'D1 command "0" data*2 0 0 Command other than H'FF 1 and H'D1 H'D1 command 0 Command other than H'D1 1 H'D1 command H'D1 command H'D1 command Any data H'D1 command 0 0 0 0 0 Notes: 1. 2. Arbitrary data with bit 1 set to 1. Arbitrary data with bit 1 cleared to 0. 254 12.4 12.4.1 Interrupts IBF1, IBF2 The host interface can request two interrupts to the slave CPU: IBF1 and IBF2. They are input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is enabled when the corresponding enable bit is set (table 12-8). Table 12-8 Input Buffer Full Interrupts Interrupt IBF1 IBF2 Description Requested when IBFIE1 is set to 1 and IDR1 is full Requested when IBFIE2 is set to 1 and IDR2 is full 12.4.2 HIRQ 11, HIRQ1, and HIRQ12 In slave mode (when HIE = 1 in SYSCR), three bits in the port 4 data register (P4DR) can be used as host interrupt request latches. These three P4DR bits are cleared to 0 by the host processor's read signal (IOR). If CS1 and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In processing the interrupt, the host's interrupt-handling routine reads the output data register (ODR1 or ODR2), and this clears the host interrupt latch to 0. Table 12-9 indicates how these bits are set and cleared. Figure 12-3 shows the processing in flowchart form. Table 12-9 Host Interrupt Set/Clear Conditions Host Interrupt Signal HIRQ11 (P4 3) HIRQ1 (P4 4) HIRQ12 (P4 5) Setting Condition Slave CPU reads 0 from P4DR bit 3, then writes 1 Slave CPU reads 0 from P4DR bit 4, then writes 1 Slave CPU reads 0 from P4DR bit 5, then writes 1 Clearing Condition Slave CPU writes 0 in P4DR bit 3, or host reads output data register 2 Slave CPU writes 0 in P4DR bit 4, or host reads output data register 1 Slave CPU writes 0 in P4DR bit 5, orhost reads output data register 1 255 Slave CPU Master CPU Write to ODR Write 1 to P4DR HIRQ output high HIRQ output low P4DR = 0? Yes All bytes transferred? Yes Interrupt initiation ODR read No No Hardware operations Software operations Figure 12-3 HIRQ Output Flowchart 12.5 Application Note The host interface provides buffering of asynchronous data from the host and slave processors, but an interface protocol must be followed to implement necessary functions and avoid data contention. For example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective protocol. 256 Section 13 RAM 13.1 Overview The H8/3502 have 512 bytes. The on-chip RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM occupies addresses H'FD80 to H'FF7F in the chip's address space. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. 13.2 Block Diagram Figure 13-1 is a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FD80 H'FD82 H'FD81 H'FD83 On-chip RAM H'FF7E Even addresses H'FF7F Odd addresses Figure 13-1 Block Diagram of On-Chip RAM 257 13.3 RAM Enable Bit (RAME) The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control register (SYSCR). Table 13-1 lists information about the system control register. Table 13-1 System Control Register Name System control register Abbreviation SYSCR R/W R/W Initial value H'09 Address H'FFC4 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See section 3.2, System Control Register for the other bits. Bit 0--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized to 1 on the rising edge of the RES signal, so a reset enables the onchip RAM. The RAME bit is not initialized in the software standby mode. Bit 7 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 13.4 13.4.1 Operation Expanded Modes (Modes 1 and 2) If the RAME bit is set to 1, accesses to addresses H'FD80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus. 13.4.2 Single-Chip Mode (Mode 3) If the RAME bit is set to 1, accesses to addresses H'FD80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, the on-chip RAM cannot be accessed. Attempted write access has no effect. Attempted read access always results in H'FF data being read. Note: Initial RAM data are unknown. Be sure to initialize when use them as control bits. 258 Section 14 ROM 14.1 Overview The H8/3502 has 16 kbytes of high-speed, on-chip ROM. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. Enabling or disabling of the on-chip ROM is determined by the inputs at the mode pins (MD1 and MD0) as shown in table 14-1. Table 14-1 On-Chip ROM Usage in Each MCU Mode Mode Pins Mode Mode 1 (expanded mode) Mode 2 (expanded mode) Mode 3 (single-chip mode) MD1 0 1 1 MD0 1 0 1 On-Chip ROM Disabled (external addresses) Enabled Enabled 259 14.1.1 Block Diagram Figure 14-1 is a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0001 H'0003 On-chip ROM H'3FFE Even addresses H'3FFF Odd addresses Figure 14-1 Block Diagram of On-Chip ROM 260 Section 15 Power-Down State 15.1 Overview The H8/3502 has a sleep mode that reduces power consumption by stopping CPU functions. Although two standby modes can be set in addition to sleep mode, use of the standby modes is not recommended since a guaranteed value is not set for current dissipation in these modes. 1. 2. 3. Sleep mode Software standby mode Hardware standby mode Table 15-1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc., in each power-down mode. Table 15-1 Power-Down State Mode Sleep mode Software standby mode Entering Procedure Execute SLEEP instruction Set SSBY bit in SYSCR to 1, then execute SLEEP instruction Clock Run CPU Halt CPU Reg's. Held Sup. Mod.* Run RAM Held I/O Ports Held Exiting Methods * Interrupt * RES * STBY * NMI * IRQ0-IRQ2 * KEYIN0- KEYIN7 * STBY * RES * STBY high, then RES low high Halt Halt Held Halt and initialized Held Held Hardware Set STBY pin standby to low level mode Halt Halt Not held Halt and initialized Held High impedance state Notes: 1. SYSCR: System control register 2. SSBY: Software standby bit * On-chip supporting modules. 261 15.1.1 System Control Register (SYSCR) Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically, they concern the software standby mode. Table 15-2 lists the attributes of the system control register. Table 15-2 System Control Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'09 Address H'FFC4 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Bit 7--Software Standby (SSBY): This bit enables or disables the transition to the software standby mode. On recovery from the software standby mode by an external interrupt SSBY remains set to 1. To clear this bit, software must write a 0. Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to the sleep mode (Initial value) The SLEEP instruction causes a transition to the software standby mode Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by means of an external interrupt. During the selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip supporting modules. Refer to table 15-3 to select an appropriate settling time for the operating frequency. 262 Bit 6 STS2 0 0 0 0 1 1 Bit 5 STS1 0 0 1 1 0 1 Bit 4 STS0 0 1 0 1 -- -- Description Settling time = 8192 states Settling time = 16384 states Settling time = 32768 states Settling time = 65536 states Settling time = 131072 states Use prohibited (Initial value) 15.2 15.2.1 Sleep Mode Transition to Sleep Mode When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The on-chip supporting modules continue to operate normally. 15.2.2 Exit from Sleep Mode The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a low input at the RES or STBY pin. (1) Wake-Up by Interrupt: An interrupt releases the sleep mode and starts the CPU's interrupthandling sequence. If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit in CCR (the condition code register) is set when the SLEEP instruction is executed. (2) Wake-Up by RES pin: When the RES pin goes low, the chip exits from the sleep mode to the reset state. (3) Wake-Up by STBY pin: When the STBY pin goes low, the chip exits from the sleep mode to the hardware standby mode. 263 15.3 15.3.1 Software Standby Mode Transition to Software Standby Mode To enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR) to 1, then execute the SLEEP instruction. In software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU registers and on-chip RAM remain unchanged. 15.3.2 Exit from Software Standby Mode The chip can be brought out of the software standby mode by an input at one of the following pins: NMI, IRQ0, to IRQ2, KEYIN0 to KEYIN7, RES, or STBY. (1) Recovery by External Interrupt: When an NMI, IRQ0, IRQ1, IRQ2 or key-sense interrupt (IRQ 6) request signal is received, the clock oscillator begins operating. After the waiting time set in the system control register (bits STS2 to STS0), clock pulses are supplied to the CPU and onchip supporting modules. The CPU executes the interrupt-handling sequence for the requested interrupt, then returns to the instruction after the SLEEP instruction. See Section 15.1.1, System Control Register, for information about the STS bits. (2) Recovery by RES Pin: When the RES pin goes low, the clock oscillator starts. Next, when the RES pin goes high, the CPU begins executing the reset sequence. The RES pin must be held low long enough for the clock to stabilize. (3) Recovery by STBY Pin: When the STBY pin goes low, the chip exits from the software standby mode to the hardware standby mode. 15.3.3 Clock Settling Time for Exit from Software Standby Mode Set bits STS2 to STS0 in SYSCR as follows: * Crystal oscillator Set STS2 to STS0 for a settling time of at least 8 ms. Table 15-3 lists the settling times selected by these bits at several clock frequencies. 264 * External clock The STS bits can be set to any value. Normally, the minimum time (STS2 = STS1 = STS0 = 0) is recommended. Table 15-3 Times Set by Standby Timer Select Bits (Unit: ms) Settling Time (States) 8,192 16,384 32,768 65,536 131,072 System Clock Frequency (MHz) 10 0.8 1.6 3.3 6.6 13.1 8 1.0 2.0 4.1 8.2 16.4 6 1.4 2.7 5.5 10.9 21.8 4 2.0 4.1 8.2 16.4 32.8 STS2 0 0 0 0 1 Notes: 1. 2. STS1 0 0 1 1 0 STS0 0 1 0 1 0 All times are in milliseconds. Recommended values are printed in boldface. 265 15.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode when NMI goes low and exits when NMI goes high, as shown in figure 15-1. The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1 (selecting the rising edge), sets SSBY to 1, then executes the SLEEP instruction. The chip enters the software standby mode. It recovers from the software standby mode on the next rising edge of NMI. Clock oscillator o NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Settling time NMI interrupt handler SLEEP Figure 15-1 Software Standby Mode NMI Timing (Example) 15.3.5 Note on Current Dissipation The I/O ports remain in their current states in software standby mode. If a port is in the high output state, it continues to dissipate power in proportion to the output current. 266 15.4 15.4.1 Hardware Standby Mode Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes low. In hardware standby mode, the functions of the CPU and all on-chip supporting modules are halted. The on-chip supporting modules are placed in the reset state, but on-chip RAM data is retained provided the minimum necessary voltage is supplied. I/O ports go to the high-impedance state. Notes: 1. The RAME bit in the system control register should be cleared to 0 before the STBY pin goes low, to disable the on-chip RAM during the hardware standby mode. 2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode. Be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in PROM mode and increases current drain. 15.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes high the clock oscillator begins running. The RES pin should be low at this time and should be held low long enough for the clock to stabilize. When the RES pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 267 15.4.3 Timing Relationships Figure 15-2 shows the timing relationships in the hardware standby mode. In the sequence shown, first RES goes low, then STBY goes low, at which point the chip enters the hardware standby mode. To recover, first STBY goes high, then after the clock settling time, RES goes high. Clock pulse generator RES STBY Clock settling time Restart Figure 15-2 Hardware Standby Mode Timing 268 Section 16 Electrical Specifications 16.1 Absolute Maximum Ratings Table 16-1 lists the absolute maximum ratings. Table 16-1 Absolute Maximum Ratings Item Supply voltage Input voltage Operating temperature Storage temperature Symbol VCC Vin Topr Tstg Rating -0.3 to +7.0 -0.3 to VCC + 0.3 -20 to +75 -55 to +125 Unit V V C C Note: Exceeding the absolute maximum ratings shown in table 16-1 can permanently damage the chip. 16.2 16.2.1 Electrical Characteristics DC Characteristics DC characteristics are shown in table 16-2, and allowable current output values in table 16-3. 269 Table 16-2 DC Characteristics Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = -20C to +75C Item Schmitt trigger input voltage P77, P75 to P7 0*2, FTCI, FTI, TMRI0, TMRI1, TMCI0, TMCI1, KEYIN7 to KEYIN0 IRQ2 to IRQ0 (1) Symbol VT- Min 1.0 Typ -- Max -- -- Preliminary -- Test Unit Conditions V VT+ -- -- VCC x 0.7 VT+ - VT- (2) VIH 0.4 VCC - 0.7 -- -- -- VCC + 0.3 V Input high RES, STBY, voltage MD1, MD0, EXTAL, NMI All input pins other than (1) and (2) above Input low voltage RES, STBY, MD1, MD0 (3) VIL 2.0 -- VCC + 0.3 -0.3 -0.3 -- -- 0.5 0.8 V All input pins other than (1) and (3) above Output high voltage All output pins VOH VCC - 0.5 3.5 -- -- -- -- -- -- 0.4 1.0 V I OH = -200 A I OH = -1.0 mA Output low All output pins voltage P17 to P1 0, P27 to P2 0, P37 to P3 0 VOL -- -- V I OL = 1.6 mA I OL = 10.0 mA 270 Table 16-2 DC Characteristics (cont) Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = -20C to +75C Item Input leakage current RES STBY, NMI, MD1, MD0 | ITS1 | Symbol | Iin | Min -- -- -- Typ -- -- -- Max 10.0 1.0 1.0 -- Preliminary -- Test Unit Conditions A Vin = 0.5 V to VCC - 0.5 V Leakage Ports 1 to 7 current in three-state (off state) Input pull- Ports 1 to 3 up MOS P73 to P7 0, current P63 to P6 0 Input capacitance RES NMI P73 to P7 0 All input pins other than (4) Current dissipation *1 Notes: 1. 2. Normal operation Sleep mode A Vin = 0.5 V to VCC - 0.5 V -I p 30 60 -- -- -- -- -- -- 23 15 250 500 60 50 20 15 40 25 A Vin = 0 V (4) Cin -- -- -- -- pF Vin = 0 V, f = 1 MHz, Ta = 25C I CC -- -- mA f = 10 MHz f = 10 MHz Value when V IH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are unloaded, and input MOS pull-ups are off. P77 and P75 to P7 0 do not include HA 0, IOW, CS 1, and WAIT. 271 Table 16-3 Allowable Output Current Values Conditions: VCC = 4.5 V to 5.5 V, VSS = 0 V, Ta = -20C to +75C Item Allowable output low current (per pin) Allowable output low current (total) Ports 1, 2 and 3 Other output pins Ports 1, 2 and 3 total Total of all output Allowable output high current (per pin) Allowable output high current (total) All output pins Total of all output -I OH -IOH IOL Symbol I OL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- -- Preliminary -- Max 10 2 80 120 2 40 Unit mA mA mA mA Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current values in table 16-3. In particular, when driving a Darlington transistor or LED direrctly, be sure to insert a current-limiting resistor in the output path. See figures 16-1 and 16-2. H8/3502 2 k Port Darlington transistor Figure 16-1 Example of Circuit for Driving a Darlington Transistor 272 H8/3502 VCC 600 Ports 1, 2 or 3 LED Figure 16-2 Example of Circuit for Driving an LED 16.2.2 AC Characteristics The AC characteristics are listed in five tables. Bus timing parameters are given in table 16-4, control signal timing parameters in table 16-5, timing parameters of the on-chip supporting modules in table 16-6, External Clock Output Settling Delay Time in table 16-7. 273 Table 16-4 Bus Timing Condition: -- Preliminary -- VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 4.0 MHz to maximum operating frequency, Ta = -20C to +75C 10 MHz Item Clock cycle time Clock pulse width low Clock pulse width high Clock rise time Clock fall time Address delay time Address hold time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width* Address setup time 1* Address setup time 2* Read data setup time Read data hold time* Read data access time* Write data delay time Write data setup time Write data hold time Wait setup time Wait hold time Symbol t cyc t CL t CH t Cr t Cf t AD t AH t ASD t WSD t SD t WSW t AS1 t AS2 t RDS t RDH t ACC t WDD t WDS t WDH t WTS t WTH Min 100 35 35 -- -- -- 20 -- -- -- 120 15 65 35 0 -- -- 5 20 40 10 Max 250 -- -- 15 15 50 -- 40 50 50 -- -- -- -- -- 170 75 -- -- -- -- Unit ns Test Conditions Fig. 16-4 Fig. 16-5 Note: * Values at maximum operating frequency 274 Table 16-5 Condition: Control Signal Timing -- Preliminary -- VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 4.0 MHz to maximum operating frequency, Ta = -20C to +75C 10 MHz Item RES setup time RES pulse width NMI setup time (NMI, IRQ0 to IRQ2, IRQ6) NMI hold time (NMI, IRQ0 to IRQ2, IRQ6) Interrupt pulse width for recovery from software standby mode (NMI, IRQ0 to IRQ2, IRQ6) Crystal oscillator settling time (reset) Crystal oscillator settling time (software standby) Symbol t RESS t RESW t NMIS t NMIH t NMIW Min 200 10 150 Max -- -- -- Unit ns t cyc ns Test Conditions Fig. 16-6 Fig. 16-7 10 -- 200 -- t OSC1 t OSC2 20 8 -- -- ms Fig. 16-8 Fig. 16-9 Measurement Conditions for AC Characteristics 5V RL LSI output pin 90 pF: P1, P2, P3, P46, P6, P7 30 pF: P4 (except P46), P5 RL = 2.4 k RH = 12 k C= C RH Input/output timing measurement levels Low: 0.8 V High: 2.0 V Figure 16-3 Test Conditions for AC Characteristics 275 Table 16-6 Condition: Timing Conditions of On-Chip Supporting Modules -- Preliminary -- VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 4.0 MHz to maximum operating frequency, Ta = -20C to +75C 10 MHz Item FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width (single edge) Timer clock pulse width (both edges) SCI Input clock cycle (Async) (Sync) Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time (Sync) Input clock pulse width Symbol t FTOD t FTIS t FTCS t FTCWH t FTCWL t TMOD t TMRS t TMCS t TMCWH t TMCWL Min -- 50 50 1.5 -- 50 50 1.5 2.5 Max 100 -- -- -- 100 -- -- -- -- -- -- 100 -- -- 0.6 Unit ns Test Conditions Fig. 16-10 Fig. 16-11 t cyc ns Fig. 16-12 Fig. 16-14 Fig. 16-13 t cyc t Scyc 4 6 t cyc Fig. 16-15 t TXD t RXS t RXH t SCKW -- 100 100 0.4 ns t Scyc Fig. 16-16 276 Table 16-6 Condition: Timing Conditions of On-Chip Supporting Modules (cont) -- Preliminary -- VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 4.0 MHz to maximum operating frequency, Ta = -20C to +75C 10 MHz Item PORT Output data delay time Input data setup time Input data hold time HIF read cycle CS/HA0 setup time CS/HA0 hold time IOR pulse width HDB delay time HDB hold time HIRQ delay time HIF write cycle CS/HA0 setup time CS/HA0 hold time IOW pulse width HDB setup time HDB hold time GA20 delay time Symbol t PWD t PRS t PRH t HAR t HRA t HRPW t HRD t HRF t HIRQ t HAW t HWA t HWPW t HDW t HWD t HGA Min -- 50 50 10 10 120 -- 0 -- 10 10 60 30 15 -- Max 100 -- -- -- -- -- 100 25 120 -- -- -- -- -- 90 Unit ns Test Conditions Fig. 16-17 ns Fig. 16-18 ns Fig. 16-19 Table 16-7 External Clock Output Settling Delay Time -- Preliminary -- Conditions: VCC = 4.5 V to 5.5 V, VSS = 0 V, Ta = -20C to +75C Item External clock output settling delay time Symbol t DEXT * Min 500 Max -- Unit s Notes Figure 16-20 Note: * tDEXT includes a 10 t cyc RES pulse width (t RESW). 277 16.3 MCU Operational Timing This section provides the following timing charts: 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 Bus Timing Control Signal Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing Serial Communication Interface Timing I/O Port Timing Host Interface Timing External Clock Ouptput Timing Figures 16-4 and 16-5 Figures 16-6 to 16-9 Figures 16-10 and 16-11 Figures 16-12 to 16-14 Figures 16-15 and 16-16 Figure 16-17 Figure 16-18 and 16-19 Figure 16-20 278 16.3.1 Bus Timing (1) Basic Bus Cycle (without Wait States) in Expanded Modes T1 tcyc tCH o tAD A15 to A0 tASD tAS1 AS, RD tACC D7 to D0 (read) tAS2 WR tWDD D7 to D0 (write) tWDS tCf tCr tCL T2 T3 tSD tAH tRDS tRDH tWSD tWSW tSD tAH tWDH Figure 16-4 Basic Bus Cycle (without Wait States) in Expanded Modes 279 (2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes T1 T2 T3 T4 o A15 to A0 AS, RD D7 to D0 (read) WR D7 to D0 (write) tWTS WAIT tWTH tWTS tWTH Figure 16-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes 280 16.3.2 Control Signal Timing (1) Reset Input Timing o tRESS RES tRESW tRESS Figure 16-6 Reset Input Timing (2) Interrupt Input Timing o tNMIS tNMIH NMI, IRQE tNMIS IRQL Note: i = 0 to 2, 6; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed tNMIW NMI, IRQi Figure 16-7 Interrupt Input Timing 281 (3) Clock Settling Timing o VCC STBY tOSC1 tOSC1 RES Figure 16-8 Clock Settling Timing (4) Clock Settling Timing for Recovery from Software Standby Mode o NMI IRQi (i = 0 to 2, 6) tOSC2 Figure 16-9 Clock Settling Timing for Recovery from Software Standby Mode 282 16.3.3 16-Bit Free-Running Timer Timing (1) Free-Running Timer Input/Output Timing o Free-running counter Compare-match tFTOD FTOA, FTOB tFTIS FTI Figure 16-10 Free-Running Timer Input/Output Timing (2) External Clock Input Timing for Free-Running Timer o tFTCS FTCI tFTCWL tFTCWH Figure 16-11 External Clock Input Timing for Free-Running Timer 283 16.3.4 8-Bit Timer Timing (1) 8-Bit Timer Output Timing o Timer counter Compare-match tTMOD TMO1, TMO0 Figure 16-12 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing o tTMCS TMCI1, TMCI0 tTMCWL tTMCWH tTMCS Figure 16-13 8-Bit Timer Clock Input Timing 284 (3) 8-Bit Timer Reset Input Timing o tTMRS TMRI1, TMRI0 Timer counter N H'00 Figure 16-14 8-Bit Timer Reset Input Timing 16.3.5 Serial Communication Interface Timing (1) SCI Input/Output Timing tScyc Serial clock SCK1, SCK0 tTXD Transmit data TxD1, TxD0 tRXS tRXH Receive data RxD1, RxD0 Figure 16-15 SCI Input/Output Timing (Synchronous Mode) 285 (2) SCI Input Clock Timing tSCKW SCK1, SCK0 tScyc Figure 16-16 SCI Input Clock Timing 16.3.6 I/O Port Timing T1 T2 T3 o tPRS Port 1 to port 7 (input) tPWD Port 1 to port 7* (output) tPRH Note: * Except P46 Figure 16-17 I/O Port Input/Output Timing 286 16.3.7 Host Interface Timing (1) Host Interface Read Timing CS/HA0 HA0 tHAR IOR tHRF tHRD HDB7 to HDB0 Effective data tHIRQ HIRQi* (i = 1, 11, 12) Note: * Rising edge timing is the same as in port 4 output timing. Refer to figure 19-18. tHRPW tHRA Figure 16-18 Host Interface Read Timing (2) Host Interface Write Timing CS/HA0 HA0 tHAW IOW tHWD tHWPW tHWA tHDW HDB7 to HDB0 tHGA GA20 Figure 16-19 Host Interface Write Timing 287 16.3.8 External Clock Output Timing VCC 4.5 V STBY VIH EXTAL o (internal and external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). Figure 16-20 External Clock Output Settling Delay Timing 288 Appendix A Instruction Set A.1 Instruction List Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx:3/8/16 d:8/16 @aa:8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not Condition Code Notation * 0 -- Modified according to the instruction result Undetermined (unpredictable) Always cleared to 0 Not affected by the instruction result 289 Table A-1 Instruction Set Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* IHNZVC @@aa -- ---- MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd16 W Rs16 Rd16 W @Rs16 Rd16 Rn 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP 290 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* 2 2 2 2 2 2 2 2 2 2 2 2 2 IHNZVC @@aa -- ---- PUSH Rs MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd W SP-2 SP Rs16 @SP B Not supported B Not supported B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8+C Rd8 B Rd8+Rs8+C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8-C Rd8 B Rd8-Rs8-C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd8 Rd8 B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rn 2 0--6 -- -- -- (1) -- -- (2) (2) ------------ 2 ------------ 2 ---- --* -- --2 * (3) 2 -- (1) -- -- (2) (2) ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 -- (1) -- -- -- -- -- -- 14 291 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* 2 2 2 2 2 2 2 2 IHNZVC @@aa -- ---- DIVXU.B Rs, Rd B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8 Rd8 B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 2 2 2 2 Rn -- -- (6) (7) -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd 0--2 0--2 0--2 0--2 0--2 0--2 0--2 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ---- SHAR.B Rd B 2 ---- 0 SHLL.B Rd B C 2 ---- 0 SHLR.B Rd B 0 2 ---- 0 0 ROTXL.B Rd B C b7 b0 C b7 b0 2 ---- 0 ROTXR.B Rd B 2 ---- 0 ROTL.B Rd B C b7 b0 C b7 b0 2 ---- 0 ROTR.B Rd B 2 ---- 0 292 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* IHNZVC @@aa -- BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 Rn ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------ ---- 2 ------ ---- 6 ------ ---- 6 ------ ---- 2 293 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 IHNZVC @@aa -- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C 2 2 2 2 2 2 2 2 Rn 4 4 ------ ---- 6 ------ ---- 6 4 4 4 4 ------------ 2 4 4 ------------ 8 ------------ 8 ------------ 2 4 4 ------------ 8 ------------ 8 4 4 4 4 4 4 4 4 294 Table A-1 Instruction Set (cont) Operation Operand Size Addressing Mode/ Instruction Length (Bytes) @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* 2 6 6 2 6 6 Mnemonic #xx:8/16 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 @@aa -- ---------- ---------- ---------- ---------- ---------- ---------- 2 Branching Condition IHNZVC 2 4 4 2 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 Rn ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 6 ------------ 8 -- PC Rn16 -- PC aa:16 -- PC @aa:8 295 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* 2 2 2 2 2 IHNZVC @@aa -- 2 2 BSR d:8 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 -- SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transition to power-down state B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 2 2 2 2 2 2 2 Rn 2 ------------ 6 JSR @Rn ------------ 6 JSR @aa:16 4 ------------ 8 JSR @@aa:8 ------------ 8 RTS RTE 2 ------------ 8 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP 2 ------------ 2 ------------ 2 2 ------------ 2 296 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Mnemonic Operation #xx:8/16 @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @Rn @(d:16, Rn) Condition Code No. of States* IHNZVC @@aa -- Rn EEPMOV -- if R4L0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; 4 -- -- -- -- -- -- (4) Notes: The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained: otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. (4) The number of states required for execution is 4n + 8 (n = value of R4L). (5) These instructions are not supported by the H8/3502. (6) Set to 1 if the divisor is negative: otherwise cleared to 0. (7) Cleared to 0 if the divisor is not zero; set to 1 if the divisor is zero. 297 A.2 Operation Code Map Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 298 Low 2 STC LDC CMP SUBX ORC ROTXL ROTXR OR XOR AND SUB DEC SUBS ROTL ROTR NEG NOT XORC ANDC LDC ADD INC ADDS MOV ADDX 3 4 5 6 7 8 9 A B C D E F DAA DAS High 0 1 Table A-2 0 NOP SLEEP SHLL SHLR 1 SHAL SHAR 2 MOV 3 BHI BLS RTS BSR RTE JMP BCC*2 BCS*2 BNE BEQ BVC BVS BPL BMI BGE 4 BRA*2 BRN*2 BLT BGT JSR BLE 5 BST Operation Code Map MULXU DIVXU 6 BCLR BTS BOR BXOR BAND MOV BIOR BIXOR BIAND BILD BIST BLD MOV*1 BSET BNOT 7 ADD EEPMOV Bit manipulation instructions 8 ADDX 9 CMP A SUBX B C OR D XOR E AND F MOV Notes: 1. The PUSH and POP instructions are identical in machine language to MOV instructions. 2. The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively. 299 A.3 Number of States Required for Execution The tables below can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x S I + J x S J + K x S K + L x S L + M x S M + N x S N Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. BSET #0, @FFC7 From table A-4: I = L = 2, J = K = M = N= 0 From table A-3: SI = 8, SL = 3 Number of states required for execution: 2 x 8 + 2 x 3 =22 JSR @@30 From table A-4: I = 2, J = K = 1, L = M = N = 0 From table A-3: SI = SJ = SK = 8 Number of states required for execution: 2 x 8 + 1 x 8 + 1 x 8 = 32 Number of States Taken by Each Cycle in Instruction Execution Access location On-Chip Memory SI SJ SK SL SM SN 1 3 6 1 3+m 6 + 2m 1 2 On-Chip Reg. Field -- External Memory 6 + 2m 2. Table A-3 Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: m: Number of wait states inserted in access to external device. 300 Table A-4 Number of Cycles in Each Instruction Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX ADDS.W #1/2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 Instruction Fetch I 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Internal Operation N AND 1 1 301 Table A-4 Number of Cycles in Each Instruction (cont) Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 Internal Operation N 2 2 2 2 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 2 302 Table A-4 Number of Cycles in Each Instruction (cont) Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BSR BST BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV Instruction Fetch I 1 2 2 1 2 2 1 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 1 2 Internal Operation N 1 1 2 2 2 2 1 2 2 1 1 1 1 1 1 12 2n + 2* 1 303 Table A-4 Number of Cycles in Each Instruction (cont) Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic INC JMP INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16,Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd Instruction Fetch I 1 2 2 2 2 2 2 1 1 1 1 1 2 1 1 2 1 2 1 1 2 2 1 1 Internal Operation N 2 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 2 2 MOV.W @(d:16, Rs), Rd 2 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd 1 2 1 MOV.W Rs, @(d:16, Rd) 2 MOV.W Rs, @-Rd MOV.W Rs, @aa:16 1 2 304 Table A-4 Number of Cycles in Each Instruction (cont) Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic MOVFPE MOVTPE MULXU NEG NOP NOT OR MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC POP PUSH ROTL ROTR ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB ORC #xx:8, CCR POP Rd PUSH Rd ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBX SUBS.W #1/2, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd Instruction Fetch I Not supported Not supported 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 Internal Operation N 12 1 1 2 2 2 1 2 2 305 Table A-4 Number of Cycles in Each Instruction (cont) Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Mnemonic XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR Instruction Fetch I 1 1 1 Internal Operation N Note: All values left blank are zero. * n: Initial value in R4L. Source and destination are accessed n + 1 times each. 306 Appendix B Internal I/O Register B.1 Addresses B.1.1 I/O Registers Address (Last Register Byte) Name Bit 7 H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 TCR TCSR FRCH FRCL OCRAH OCRAL OCRBH OCRBL ICRH ICRL ICIE ICF OCIEB OCFB OCIEA OCFA OVIE OVF OEB OLVLB OEA OLVLA CKS1 IEDG CKS0 CCLRA FRT Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name External memory (in expanded modes) 307 Address (Last Register Byte) Name Bit 7 H'9A H'9B H'9C H'9D H'9E H'9F H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 HB2 H'B3 H'B4 H'B5 H'B6 H'B7 P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR TCSR/ TCNT TCNT P1PCR P2PCR P3PCR OVF Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name WT/IT TME -- RST/ NMI CKS2 CKS1 CKS0 WDT P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 P17 P27 P16 P26 P15 P25 P14 P24 P13 P23 P12 P22 P11 P21 P10 P20 Port 1 Port 2 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 P37 P47 P36 P46 P35 P45 P34 P44 P33 P43 P32 P42 P31 P41 P30 P40 Port 3 Port 4 308 Address (Last Register Byte) Name Bit 7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 TCR TCSR TCORA TCORB TCNT CMIEB CMFB WSCR STCR SYSCR MDCR ISCR IER TCR TCSR TCORA TCORB TCNT -- (IICS) SSBY -- -- -- CMIEB CMFB P5DDR P6DDR P5DR P6DR P7DDR -- P7DR -- -- -- -- -- Bit Names Bit 6 -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Port 5 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 -- P66 P55 P65 P54 P64 P53 P63 P52 P62 P51 P61 P50 P60 Port 5 Port 6 P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Port 7 -- P77 -- -- P76 -- -- P75 -- -- P74 -- -- P73 -- -- P72 -- -- P71 -- -- P70 -- -- Port 7 -- -- (IICX1) STS2 -- CLKDBL -- (IICX0) STS1 -- WMS1 WMS0 WC1 WC0 ICKS0 RAME MDS0 (SYNCE) (PWCKE) (PWCKS) ICKS1 STS0 -- -- -- CCLR1 PWME XRST -- -- -- CCLR0 OS3 NMIEG -- HIE MDS1 IRQ6SC -- IRQ6E CMIEA CMFA -- OVIE OVF IRQ2SC IRQ1SC IRQ0SC IRQ2E CKS2 OS2 IRQ1E CKS1 OS1 IRQ0E CKS0 OS0 TMR0 CMIEA CMFA OVIE OVF CCLR1 PWME CCLR0 OS3 CKS2 OS2 CKS1 OS1 CKS0 OS0 TMR1 309 Address (Last Register Byte) Name Bit 7 H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF SMR BRR SCR TDR SSR RDR SCMR -- SMR BRR SCR TDR SSR RDR -- -- -- -- TDRE TIE -- -- C/A TDRE TIE C/A Bit Names Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI0 RIE TE RE MPIE TEIE CKE1 CKE0 RDRF ORER FER PER TEND MPB MPBT -- -- CHR -- -- PE -- -- O/E SDIR -- STOP SINV -- MP -- -- CKS1 SMIF -- CKS0 SCI1 RIE TE RE MPIE TEIE CKE1 CKE0 RDRF ORER FER PER TEND MPB MPBT -- -- -- -- -- -- -- -- -- -- -- -- -- -- 310 Address (Last Register Byte) Name Bit 7 H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF HICR KMIMR KMPCR -- IDR1 ODR1 STR1 -- -- -- -- -- IDR2 ODR2 STR2 -- -- Bit Names Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 IBFIE2 Bit 1 IBFIE1 Bit 0 Module Name FGA20E HIF KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Port 6/ Port 7 -- IDR7 ODR7 DBU -- -- -- -- -- IDR7 ODR7 DBU -- -- IDR6 ODR6 DBU -- -- -- -- -- IDR6 ODR6 DBU -- -- IDR5 ODR5 DBU -- -- -- -- -- IDR5 ODR5 DBU -- -- IDR4 ODR4 DBU -- -- -- -- -- IDR4 ODR4 DBU -- -- IDR3 ODR3 C/D -- -- -- -- -- IDR3 ODR3 C/D -- -- IDR2 ODR2 DBU -- -- -- -- -- IDR2 ODR2 DBU -- -- IDR1 ODR1 IBF -- -- -- -- -- IDR1 ODR1 IBF -- -- IDR0 ODR0 OBF -- -- -- -- -- IDR0 ODR0 OBF -- HIF Notes: FRT: Free-running timer TMR0: 8-bit timer channel 0 TMR1: 8-bit timer channel 1 SCI0: Serial communication interface 0 SCI1: Serial communication interface 1 HIF: Host interface 311 B.2 Function Address onto which register is mapped Register name Abbreviation of register name TCR--Timer Control Register H'90 Name of on-chip supporting module FRT Bit No. Initial value Bit Initial value Read/Write 7 ICIE 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit names (abbreviations). Bits marked "--" are reserved. Type of access permitted R Read only W Write only R/W Read or write Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Output Enable A 0 Output compare A output is disabled 1 Output compare A output is enabled Output Enable B 0 Output compare B output is disabled 1 Output compare B output is enabled Timer Overflow Interrupt Enable 0 Timer overflow interrupt request (FOVI) is disabled 1 Timer overflow interrupt request (FOVI) is enabled Full name of bit Description of bit function 312 TCR--Timer Control Register Bit Initial value Read/Write 7 ICIE 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W H'90 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 FRT CKS0 0 R/W Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Output Enable A 0 Output compare A output is disabled 1 Output compare A output is enabled Output Enable B 0 Output compare B output is disabled 1 Output compare B output is enabled Timer Overflow Interrupt Enable 0 Timer overflow interrupt request (FOVI) is disabled 1 Timer overflow interrupt request (FOVI) is enabled Output Compare Interrupt Enable A 0 Output compare interrupt request A (OCIA) is disabled 1 Output compare interrupt request A (OCIA) is enabled Output Compare Interrupt Enable B 0 Output compare interrupt request B (OCIB) is disabled 1 Output compare interrupt request B (OCIB) is enabled Input Capture Interrupt Enable 0 Input capture interrupt request (ICI) is disabled 1 Input capture interrupt request (ICI) is enabled 313 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 ICF 0 R/(W) * 6 OCFB 0 R/(W) * 5 OCFA 0 R/(W) * 4 OVF 0 H'91 3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W 0 FRT CCLRA 0 R/W R/(W) * Counter Clear A 0 The FRC is not cleared 1 The FRC is cleared at compare-match A Input Edge Select 0 FRC contents are transferred to ICR on the falling edge of FTI 1 FRC contents are transferred to ICR on the rising edge of FTI Output Level A 0 A 0 logic level is output for compare-match A 1 A 1 logic level is output for compare-match A Output Level B 0 A 0 logic level is output for compare-match B 1 A 1 logic level is output for compare-match B Timer Overflow 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when FRC changes from H'FFFF to H'0000 Output Compare Flag A 0 To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when FRC = OCRA Output Compare Flag B 0 To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when FRC = OCRB Input Capture Flag 0 To clear ICF, the CPU must read ICF after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when an FTI input signal causes the FRC value to be copied to the ICR Note: * Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits. 314 FRC (H and L)--Free-Running Counter Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'92, H'93 7 0 6 0 5 0 4 0 3 0 2 0 1 0 FRT 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA (H and L)--Output Compare Register A Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'94, H'95 FRT 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA is constantly compared with the FRC value, and the OCFA bit is set to 1 when OCRA = FRC OCRB (H and L)--Output Compare Register B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'96, H'97 FRT 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRB is constantly compared with the FRC value, and the OCFB bit is set to 1 when OCRB = FRC 315 ICR (H and L)--Input Capture Register Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'98, H'99 7 0 6 0 5 0 4 0 3 0 2 0 1 0 FRT 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Contains FRC count captured on FTI input 316 TCSR/TCNT--Timer Control/Status Register Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- H'AA WDT 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock Select 2 to 0 CKS2 CKS1 CKS0 Clock Source 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 Overflow Interval (oP = 10 MHz) 51.2 s (Initial value) 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms Reset or NMI Select 0 NMI function enabled 1 Reset function enabled Timer Enable 0 TCNT is initialized to H'00 and stopped (Initial value) 1 TCNT runs and requests a reset or interrupt when it overflows Timer Mode Select 0 Interval timer mode (OVF request) 1 Watchdog timer mode (reset or NMI request) Overflow Flag 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) 1 Set to 1 when TCNT changes from H'FF to H'00 (Initial value) (Initial value) 317 TCNT--Timer Counter H'AB (read) H'AA (write) 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Bit Initial value Read/Write 7 0 R/W R/W Count value P1PCR--Port 1 Pull-Up MOS Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'AC P1 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1 Input Pull-Up Control 0 Input pull-up transistor is off 1 Input pull-up transistor is on P2PCR--Port 2 Pull-Up MOS Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'AD P2 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2 Input Pull-Up Control 0 Input pull-up transistor is off 1 Input pull-up transistor is on 318 P3PCR--Port 3 Pull-Up MOS Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'AE P3 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3 Input Pull-Up Control 0 Input pull-up transistor is off 1 Input pull-up transistor is on P1DDR--Port 1 Data Direction Register Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 7 6 5 4 H'B0 3 2 1 0 P1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W 1 -- 0 W Port 1 Input/Output Control 0 Input port 1 Output port P1DR--Port 1 Data Register Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W H'B2 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W P1 319 P2DDR--Port 2 Data Direction Register Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 7 6 5 4 H'B1 3 2 1 0 P2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W 1 -- 0 W Port 2 Input/Output Control 0 Input port 1 Output port P2DR--Port 2 Data Register Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W H'B3 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W P2 320 P3DDR--Port 3 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'B4 3 0 W 2 0 W 1 0 W 0 0 W P3 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 Input/Output Control 0 Input port 1 Output port P3DR--Port 3 Data Register Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W H'B6 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W P3 321 P4DDR--Port 4 Data Direction Register Bit Modes 1 and 2 Initial value Read/Write Mode 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 1 -- 0 W 0 W 7 6 5 4 H'B5 3 2 1 0 P4 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 4 Input/Output Control 0 Input port 1 Output port P4DR--Port 4 Data Register Bit Initial value Read/Write 7 P47 0 R/W 6 P46 --* R/W 5 P45 0 R/W 4 P44 0 R/W H'B7 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W P4 Note: * Depends on the state of the P46 pin. 322 P5DDR--Port 5 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W H'B8 3 0 W 2 0 W 1 0 W 0 0 W P5 P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Port 5 Input/Output Control 0 Input port 1 Output port P5DR--Port 5 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 P55 0 R/W 4 P54 0 R/W H'BA 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W P5 P6DDR--Port 6 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 0 W 5 0 W 4 0 W H'B9 3 0 W 2 0 W 1 0 W 0 0 W P6 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 Input/Output Control 0 Input port 1 Output port 323 P6DR--Port 6 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W H'BB 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W P6 P7DDR--Port 7 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'BC 3 0 W 2 0 W 1 0 W 0 0 W P7 P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Port 7 Input/Output Control 0 Input port 1 Output port P7DR--Port 7 Data Register Bit Initial value Read/Write 7 P77 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W H'BE 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W P7 324 WSCR--Wait State Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 0 R/W H'C2 3 WMS1 1 R/W 2 WMS0 0 R/W 1 System Control 0 WC0 0 R/W WC1 0 R/W Wait Count 1 and 0 0 0 No wait states inserted by wait state controller 1 1 state inserted 1 0 2 states inserted 1 3 states inserted Wait Mode Select 1 and 0 0 0 Programmable wait mode 1 No wait states inserted by wait state controller 1 0 Pin wait mode 1 Pin auto-wait mode Clock Double 0 The undivided system clock (o) is supplied as the clock (op) for supporting modules (Initial value) 1 The system clock (o) is divided by two and supplied as the clock (op) for supporting modules (Initial value) (Initial value) 325 STCR--Serial Timer Control Register Bit Initial value Read/Write 7 (IICS) 0 R/W 6 (IICX1) 0 R/W 5 0 R/W 4 0 R/W H'C3 3 0 R/W 2 0 R/W 1 0 R/W 0 ICKS0 0 R/W (IICX0) (SYNCE) (PWCKE) (PWCKS) ICKS1 Internal Clock Select 1 and 0 See TCSR for details. Note: The IICS, IICX1, IICX0, SYNCE, PWCKE, and PWCKS bits must not be used (must not be set to 1). 326 SYSCR--System Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'C4 3 XRST 1 R 2 NMIEG 0 R/W 1 System Control 0 RAME 1 R/W HIE 0 R/W RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled Host Interface Enable 0 Host interface is disabled (initial value) 1 Host interface is enabled (slave mode) NMI Edge 0 Falling edge of NMI is detected 1 Rising edge of NMI is detected External Reset 0 Reset was caused by watchdog timer overflow. 1 Reset was caused by external input (Initial value) Standby Timer Select 2 to 0 0 0 0 Clock settling time = 8,192 states 0 0 1 Clock settling time = 16,384 states 0 1 0 Clock settling time = 32,768 states 0 1 1 Clock settling time = 65,536 states 1 0 -- Clock settling time = 131,072 states 1 1 -- Unused Software Standby 0 SLEEP instruction causes transition to sleep mode 1 SLEEP instruction causes transition to software standby mode 327 MDCR--Mode Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 -- H'C5 3 -- 0 -- 2 -- 1 -- 1 System Control 0 MDS0 --* R MDS1 --* R Mode Select Mode pin values Note: * Initialized according to MD1 and MD0 inputs. ISCR--IRQ Sense Control Register Bit Initial value Read/Write 7 -- 1 -- 6 IRQ6SC 0 R/W 5 -- 1 -- 4 -- 1 -- H'C6 3 -- 1 -- 2 0 R/W 1 0 System Control 0 0 R/W IRQ2SC IRQ1SC IRQ0SC R/W IRQ0 Sense Control IRQOSC 0 1 IRQ1 Sense Control IRQ1SC 0 1 Description The low level of IRQ1 generates an interrupt request The falling edge of IRQ1 generates an interrupt request Description The low level of IRQ0 generates an interrupt request The falling edge of IRQ0 generates an interrupt request IRQ2 Sense Control IRQ2SC 0 1 Description The low level of IRQ2 generates an interrupt request The falling edge of IRQ2 generates an interrupt request IRQ6 Sense Control IRQ6SC 0 1 Description The low level of KEYIN0 to KEYIN7 generates an interrupt request The falling edge of KEYIN0 to KEYIN7 generates an interrupt request 328 IER--IRQ Enable Register Bit Initial value Read/Write 7 -- 1 -- 6 IRQ6E 0 R/W 5 -- 1 -- 4 -- 1 -- H'C7 3 -- 1 -- 2 IRQ2E 0 R/W IRQ Enable 1 System Control 0 IRQ0E 0 R/W IRQ1E 0 R/W IRQ Enable 0 IRQ6 is disabled 1 IRQ6 is enabled 0 IRQ0/IRQ1/IRQ2 is disabled 1 IRQ0/IRQ1/IRQ2 is enabled 329 TCR--Timer Control Register Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 H'C8 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W TMR0 0 CKS0 0 R/W CCLR1 0 R/W Clock Select 2 to 0 Channel 0 TCR STCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 CKS2 CKS1 CKS0 ICKS1 ICKS0 0 0 0 -- -- 0 0 1 -- 0 0 0 1 -- 1 0 1 0 -- 0 0 1 0 -- 1 0 1 1 -- 0 0 1 1 -- 1 1 0 0 -- -- 1 0 1 -- -- 1 1 0 -- -- 1 1 1 -- -- 0 0 0 -- -- 0 0 1 0 -- 0 0 1 1 -- 0 1 0 0 -- 0 1 0 1 -- 0 1 1 0 -- 0 1 1 1 -- 1 0 0 -- -- 1 0 1 -- -- 1 1 0 -- -- 1 1 1 -- -- Description No clock source (timer stopped) oP/8 internal clock source, counted on the falling edge oP/2 internal clock source, counted on the falling edge oP/64 internal clock source, counted on the falling edge oP/32 internal clock source, counted on the falling edge oP/1024 internal clock source, counted on the falling edge oP/256 internal clock source, counted on the falling edge No clock source (timer stopped) External clock source, counted on the rising edge External clock source, counted on the falling edge External clock source, counted on both the rising and falling edges No clock source (timer stopped) oP/8 internal clock source, counted on the falling edge oP/2 internal clock source, counted on the falling edge oP/64 internal clock source, counted on the falling edge oP/128 internal clock source, counted on the falling edge oP/1024 internal clock source, counted on the falling edge oP/2048 internal clock source, counted on the falling edge No clock source (timer stopped) External clock source, counted on the rising edge External clock source, counted on the falling edge External clock source, counted on both the rising and falling edges 1 Counter Clear 1 and 0 0 0 1 1 0 1 0 1 Not cleared Cleared on compare-match A Cleared on compare-match B Cleared on rising edge of external reset input signal Timer Overflow Interrupt Enable 0 1 The timer overflow interrupt request (OVI) is disabled The timer overflow interrupt request (OVI) is enabled Compare-Match Interrupt Enable A 0 1 Compare-match interrupt request A (CMIA) is disabled Compare-match interrupt request A (CMIA) is enabled Compare-Match Interrupt Enable B 0 1 Compare-match interrupt request B (CMIB) is disabled Compare-match interrupt request B (CMIB) is enabled 330 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 CMFB 0 R/(W) *2 6 CMFA 0 5 OVF 0 4 H'C9 3 OS3 *1 0 R/W 2 OS2 *1 0 R/W 1 OS1*1 0 R/W TMR0 0 OS0*1 0 R/W PWME 0 R/W R/(W)*2 R/(W)*2 Output Select 1 and 0 0 0 No change when compare-match A occurs 0 1 Output changes to 0 when compare-match A occurs 1 0 Output changes to 1 when compare-match A occurs 1 1 Output inverts (toggles) when compare-match A occurs Output Select 3 and 2 0 0 No change when compare-match B occurs 0 1 Output changes to 0 when compare-match B occurs 1 0 Output changes to 1 when compare-match B occurs 1 1 Output inverts (toggles) when compare-match B occurs PWM Mode Enable 0 Normal timer mode 1 PWM mode Timer Overflow Flag 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when TCNT changes from H'FF to H'00 Compare-Match Flag A 0 To clear CMFA, the CPU must read CMFA after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when TCNT = TCORA Compare-Match Flag B 0 To clear CMFB, the CPU must read CMFB after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when TCNT = TCORB Notes: *1. When all four output select bits (bits OS3 to OS0) are cleared to 0, the timer output signal is disabled. *2. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 331 (Initial value) TCORA--Time Constant Register A Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'CA 3 1 R/W 2 1 R/W 1 1 R/W TMR0 0 1 R/W The CMFA bit is set to 1 when TCORA = TCNT TCORB--Time Constant Register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'CB 3 1 R/W 2 1 R/W 1 1 R/W TMR0 0 1 R/W The CMFB bit is set to 1 when TCORB = TCNT TCNT--Timer Counter Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'CC 3 0 R/W 2 0 R/W 1 0 R/W TMR0 0 0 R/W Count value 332 TCR--Timer Control Register Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 H'D0 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W TMR1 0 CKS0 0 R/W CCLR1 0 R/W Note: Bit functions are the same as for TMR0. TCSR--Timer Status Control Register Bit Initial value Read/Write 7 CMFB 0 R/(W) *2 6 CMFA 0 R/(W) *2 5 OVF 0 R/(W) *2 4 PWME 0 R/W H'D1 3 OS3*1 0 R/W 2 OS2 *1 0 R/W 1 OS1*1 0 R/W 0 TMR1 OS0*1 0 R/W Notes: Bit functions are the same as for TMR0. *1. When all four output select bits (bits OS3 to OS0) are cleared to 0, the timer output signal is disabled. *2. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 333 TCORA--Time Constant Register A Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'D2 3 1 R/W 2 1 R/W 1 1 R/W TMR1 0 1 R/W Note: Bit functions are the same as for TMR0. TCORB--Time Constant Register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'D3 3 1 R/W 2 1 R/W 1 1 R/W TMR1 0 1 R/W Note: Bit functions are the same as for TMR0. TCNT--Timer Counter Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'D4 3 0 R/W 2 0 R/W 1 0 R/W TMR1 0 0 R/W Note: Bit functions are the same as for TMR0. 334 SMR--Serial Mode Register Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'D8 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI0 CKS0 0 R/W Clock Select 0 0 o clock 0 1 oP/4 clock 1 0 oP/16 clock 1 1 oP/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit is added Receive: Parity is not checked 1 Transmit: A parity bit is added Receive: Parity is checked Character Length 0 8 bits per character 1 7 bits per character Communication Mode 0 Asynchronous communication 1 Synchronous communication 335 BRR--Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'D9 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 R/W Sets the bit rate TDR--Transmit Data Register 0 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'DB 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 R/W Stores transmit data 336 SCR--Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'DA 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI0 CKE0 0 R/W Clock Enable 0 0 The SCK pin is not used by the SCI 1 The SCK pin is used for serial clock output Clock Enable 1 0 Internal clock source is selected 1 External clock source is selected Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled 1 TSR-empty interrupt request is enabled Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled 1 Multiprocessor receive interrupt function is enabled Receive Enable 0 The receive function is disabled 1 The receive function is enabled Transmit Enable 0 The transmit function is disabled 1 The transmit function is enabled Receive Interrupt Enable 0 The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1 The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Transmit Interrupt Enable 0 The TDR-empty interrupt request (TXI) is disabled 1 The TDR-empty interrupt request (TXI) is enabled 337 SSR--Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'DC 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI0 MPBT 0 R/W Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data 1 Multiprocessor bit = 1 in transmit data Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data 1 Multiprocessor bit = 1 in receive data Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission Parity Error 0 To clear PER, the CPU must read PER after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in SMR) Framing Error 0 To clear FER, the CPU must read FER after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 if a framing error occurs (stop bit = 0) Overrun Error 0 To clear OER, the CPU must read OER after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1) Receive Data Register Full 0 To clear RDRF, the CPU must read RDRF after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 when one character is received without error and transferred from RSR to RDR Transmit Data Register Empty 0 To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in this bit 1 This bit is set to 1 at the following times: 1. When TDR contents are transferred to TSR 2. When the TE bit in SCR is cleared to 0 Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. 338 RDR--Receive Data register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'DD 3 0 R 2 0 R 1 0 R 0 0 R SCI0 Stores receive data SCMR--Serial Communication Mode Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'DE SCI0 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Serial Communication Mode Select 0 Normal SCI mode 1 Reserved mode Data Invert 0 TDR contents are transmitted as they are TDR contents are stored in RDR as they are (Initial value) (Initial value) 1 TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Data Transfer Direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) 339 SMR--Serial Mode Register 1 Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'E0 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'E1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 R/W Note: Bit functions are the same as for SCI0. SCR--Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'E2 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI1 CKE0 0 R/W Note: Bit functions are the same as for SCI0. 340 TDR--Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'E3 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 R/W Note: Bit functions are the same as for SCI0. SSR--Serial Status Register 1 Bit Initial value Read/Write 7 TDRE 0 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 H'E4 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI1 MPBT 0 R/W R/(W)* Note: Bit functions are the same as for SCI0. RDR--Receive Data register 1 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'E5 3 0 R 2 0 R 1 0 R 0 0 R SCI1 Note: Bit functions are the same as for SCI0. 341 HICR--Host Interface Control Register Bit Initial value Slave Read/Write Host Read/Write 7 -- 1 -- -- 6 -- 1 -- -- 5 -- 1 -- -- 4 H'F0 3 -- 1 -- -- 2 IBFIE2 0 R/W -- 1 0 R/W -- HIF 0 0 R/W -- -- 1 -- -- IBFIE1 FGA20E Fast Gate A20 Enable 0 Disables fast A20 gate function 1 Enables fast A20 gate function Input Buffer Full Interrupt Enable 1 0 IDR1 input buffer full interrupt is disabled (Initial value) 1 IDR1 input buffer full interrupt is enabled Input Buffer Full Interrupt Enable 2 0 IDR2 input buffer full interrupt is disabled (Initial value) 1 IDR2 input buffer full interrupt is enabled (Initial value) KMIMR--Keyboard Matrix Interrupt Mask Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'F1 System Control 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Keyboard Matrix Interrupt Mask 0 Key-sense input interrupt request is enabled 1 Key-sense input interrupt request is disabled (Initial value) 342 KMPCR--Key-Sense MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'F2 P6/P7 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Port 6 Input MOS Pull-Up Control 0 1 The input MOS pull-up is off The input MOS pull-up is on IDR1--Input Data Register Bit Initial value Slave Read/Write Host Read/Write 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 H'F4 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 HIF IDR4 -- R W IDR0 -- R W ODR1--Output Data Register Bit Initial value Slave Read/Write Host Read/Write 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 H'F5 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 HIF ODR4 -- R/W R ODR0 -- R/W R 343 STR1--Status Register Bit Initial value Slave Read/Write Host Read/Write 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 H'F6 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 HIF DBU 0 R/W R OBF 0 R R Output Buffer Full 0 This bit is cleared when the host processor read ODR1 1 This bit is set when the slave processor writes to ODR1 Input Buffer Full 0 This bit is cleared when the slave processor reads IDR1 (Initial value) 1 This bit is set when the host processor writes to IDR1 Command/Data 0 Contents of IDR1 are data 1 Contents of IDR1 are a command Defined by User The user can use these bits as necessary (Initial value) (Initial value) IDR2--Input Data Register Bit Initial value Slave Read/Write Host Read/Write 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 H'FC 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 HIF IDR4 -- R W IDR0 -- R W 344 ODR2--Output Data Register Bit Initial value Slave Read/Write Host Read/Write 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 H'FD 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 HIF ODR4 -- R/W R ODR0 -- R/W R STR2--Status Register Bit Initial value Slave Read/Write Host Read/Write 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 H'FE 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 HIF DBU 0 R/W R OBF 0 R R Output Buffer Full 0 This bit is cleared when the host processor read ODR1 1 This bit is set when the slave processor writes to ODR1 Input Buffer Full 0 This bit is cleared when the slave processor reads IDR1 (Initial value) 1 This bit is set when the host processor writes to IDR1 Command/Data 0 Contents of IDR1 are data 1 Contents of IDR1 are a command Defined by User The user can use these bits as necessary (Initial value) (Initial value) 345 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset Internal lower address bus R Q D P1PCR C RP1P Hardware standby WP1P Mode 1 Reset SR Q D P1nDDR C * WP1D Mode 3 Reset R Q D P1nDR C Mode 1 or 2 WP1 P1n RP1 WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 n = 0 to 7 Note: * Set priority Figure C-1 Port 1 Block Diagram 346 Internal data bus C.2 Port 2 Block Diagram Reset Internal upper address bus R Q D P2PCR C Internal data bus RP2P Hardware standby WP2P Mode 1 Reset SR Q D P2nDDR C * WP2D Mode 3 Reset R Q D P2nDR C WP2 P2n Mode 1 or 2 RP2 WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 0 to 7 Note: * Set priority Figure C-2 Port 2 Block Diagram 347 C.3 Port 3 Block Diagram HIE Mode 3 Mode 3 Reset R Q D P3nPCR C WP3P CS IOR Reset R Q D P3nDDR C Host interface data bus WP3D Reset Internal data bus RP3P External address write P3n R Q D P3nDR C Modes 1 or 2 CS IOW WP3 RP3 External address read WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 n = 0 to 7 Figure C-3 Port 3 Block Diagram 348 C.4 Port 4 Block Diagrams Reset Internal data bus 8-bit timer Timer connection Schmitt input Counter clock input Counter reset input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0, 2 R Q D P4nDDR C WP4D Reset P4n R Q D P4nDR C WP4 RP4 Figure C-4 (a) Port 4 Block Diagram (Pins P40, P42) 349 Reset Internal data bus 8-bit timer module Timer connection Output enable 8-bit timer output or HSYNCO/CLAMPO R Q D P41DDR C WP4D Reset P41 R Q D P41DR C WP4 RP4 WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C-4 (b) Port 4 Block Diagram (Pin P41) 350 Reset R Q D P4nDDR C WP4D Reset Internal data bus Reset P4n R Q D P4nDR C WP4 RESOBF2, RESOBF1 (reset HIRQ11 and HIRQ12, respectively) HIF RP4 8-bit timer Schmitt input Counter clock input Counter reset input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 3, 5 Figure C-4 (c) Port 4 Block Diagram (Pins P43, P45) 351 Reset R Q D P44DDR C WP4D HIF Internal data bus Reset R Q D P44DR C WP4 RESOBF1 (reset HIRQ1) Reset P44 8-bit timer Output enable 8-bit timer output RP4 WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C-4 (d) Port 4 Block Diagram (Pin P44) 352 Hardware standby Mode 3*HIE Mode 1, 2 Reset SR Q D P46DDR C WP4D Internal data bus P46 o RP4 HIF Input (CS2) WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C-4 (e) Port 4 Block Diagram (Pin P46) 353 Reset R Q D P47DDR C WP4D Internal data bus HIF FGA20 FGA20E P47 Reset R Q D P47DR C WP4 RP4 WP4D: DDR write WP4: Port write RP4: Port read Figure C-4 (f) Port 4 Block Diagram (Pin P47) 354 C.5 Port 5 Block Diagrams Reset R Q D P5nDDR C WP5D Internal data bus SCI Output enable Serial transmit data Reset P5n R Q D P5nDR C WP5 RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 0, 3 Figure C-5 (a) Port 5 Block Diagram (Pins P50, P53) 355 Reset R Q D P5nDDR C WP5D Reset P5n R Q D P5nDR C WP5 Internal data bus SCI Input enable Serial receive data RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 1, 4 Figure C-5 (b) Port 5 Block Diagram (Pins P51, P54) 356 Reset R Q D P5nDDR C WP5D Reset P5n R Q D P5nDR C WP5 Internal data bus SCI Clock input enable Clock output enable Clock output Clock input RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 2, 5 Figure C-5 (c) Port 5 Block Diagram (Pins P52, P55) 357 C.6 Port 6 Block Diagrams KMnPCR Reset R Q D P6nDDR C WP6D Reset P6n R Q D P6nDR C WP6 RP6 Free-running timer module Schmitt input Input capture input Counter clock input Internal data bus Key-sense interrupt input KMIMRn WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 0, 3 Figure C-6 (a) Port 6 Block Diagram (Pins P60, P63) 358 R Q D P6nDDR C WP6D Reset P6n R Q D P6nDR C WP6 Internal data bus Free-running timer module Output enable Output compare output Key-sense interrupt input KMIMRn KMnPCR Reset RP6 Schmitt input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 1, 2 Figure C-6 (b) Port 6 Block Diagram (Pins P61, P62) 359 Reset R Q D P6nDDR C WP6D Reset P6n R Q D P6nDR C WP6 RP6 Internal data bus KMIMRn IRQ0 input IRQ1 input IRQ2 input IRQ enable register IRQ0 enable IRQ1 enable IRQ2 enable Schmitt input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 4 to 6 Figure C-6 (c) Port 6 Block Diagram (Pins P64, P65, P66) 360 C.7 Port 7 Block Diagrams KMnPCR Reset Internal data bus P6mDDR KMIMRm RP6 R Q D P7nDDR C WP7D Reset P7n R Q D P7nDR C WP7 Schmitt input RP7 WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 n = 0 to 3; m = 4 to 7 (n+4) Figure C-7 (a) Port 7 Block Diagram (Pins P70, P71, P72, P73) 361 Mode 3*HIE Hardware standby Mode 1 or 2 Reset Internal data bus R Q D P7nDDR C WP7D Mode 3 P7n Mode 1 or 2 Reset R Q D P7nDR C WP7 AS output WR output Schmitt output RP7 HIF Input (CS1, IOW) WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 n = 4, 5 Figure C-7 (b) Port 7 Block Diagram (Pins P74, P75) 362 Hardware standby Mode 3*HIE Mode 1, 2 Reset Internal data bus R Q D P76DDR C WP7D Mode 3 P76 Mode 1, 2 Reset R Q D P76DR C WP7 RD output RP7 HIF WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 Input (IOR) Figure C-7 (c) Port 7 Block Diagram (Pin P76) 363 Mode 3*HIE Mode 1 or 2 Reset Internal data bus WAIT input WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 HIF Input (HA0) R Q D P77DDR C WP7D Reset P77 R Q D P77DR C WP7 Schmitt output RP7 Figure C-7 (d) Port 7 Block Diagram (Pin P77) 364 Appendix D Pin States Table D-1 Pin Name P17 to P1 0 A7 to A 0 Port States in Each Mode MCU Mode 1 2 Reset Low 3-state Hardware Standby 3-state Software Standby Low Low if DDR = 1, prev. state if DDR = 0 Prev. state Low 3-state 3-state Low Low if DDR = 1, prev. state if DDR = 0 Prev. state 3-state 3-state 3-state 3-state Prev. state (Addr. output pins: last address accessed) Sleep Mode Prev. state (Addr. output pins: last address accessed) Normal Operation A7 to A 0 Addr. output or input port 3 P27 to P2 0 A15 to A 8 1 2 I/O port A15 to A 8 Addr. output or input port 3 P37 to P3 0 D7 to D0 1 2 3 P45 to P4 0 1 2 3 P46/o 1 2 3 Clock output 3-state 3-state 3-state 3-state I/O port D7 to D0 Prev. state Prev. state (note) Prev. state Prev. state I/O port I/O port High Clock output Clock output if DDR = 1, 3-state if DDR = 0 Prev. state Clock output Clock output if DDR = 1, input port if DDR = 0 I/O port High if DDR = 1, 3-state if DDR = 0 3-state Prev. state (note) P47 1 2 3 3-state P55 to P5 0 1 2 3 3-state 3-state Prev. state (note) Prev. state I/O port 365 Table D-1 Pin Name P66 to P6 0 Port States in Each Mode MCU Mode 1 2 3 Reset 3-state Hardware Standby 3-state Software Standby Prev. state (note) Sleep Mode Prev. state Normal Operation I/O port P77/WAIT 1 2 3 3-state 3-state 3-state/prev. state Prev. state 3-state/prev. state Prev. state High WAIT/ I/O port I/O port AS, WR, RD P76 to P7 4 AS, WR, RD 1 2 3 High 3-state High 3-state 3-state 3-state Prev. state Prev. state (note) Prev. state Prev. state I/O port I/O port P73 to P7 0 1 2 3 Legend 3-state: High-impedance state Prev. state: Input pins are in the high-impedance state (for pins with a built-in MOS input pull-up the pull-up remains on when DDR = 0 and PCR = 1); output pins retain their previous state. Note: As on-chip supporting modules are initialized, general input or output is determined by DDR and DR. 366 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10 tcyc RES t2 0 ns (2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM contents, RES does not have to be driven low as in (1). Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns RES tOSC 367 Appendix F Product Code Lineup Table F-1 Product Code Lineup Product Code HD6433502P HD6433502F Mark Code HD6433502(***)P HD6433502(***)F Package (Hitachi Package Code) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) Product Type H8/3502 Mask ROM version Note: (***) in mask versions is the ROM code. 368 Appendix G Package Dimensions Figure G-1 shows the dimensions of the DP-64S package. Figure G-2 shows the dimensions of the FP-64A package. Unit: mm 64 57.6 58.5 Max 33 17.0 18.6 Max 1 1.46 Max 1.0 32 2.54 Min 5.08 Max 19.05 0.51 Min 1.78 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 Dimension including the plating thickness Base material dimension Figure G-1 Package Dimensions (DP-64S) 369 Unit: mm 17.2 0.3 14 48 49 17.2 0.3 33 32 0.8 64 1 0.37 0.08 0.35 0.06 17 16 3.05 Max 0.15 M 2.70 1.0 0.17 0.05 0.15 0.04 1.6 0 - 8 0.8 0.3 0.10 Dimension including the plating thickness Base material dimension Figure G-2 Package Dimensions (FP-64A) 370 0.10 +0.15 -0.10 H8/3502 Series Hardware Manual Publication Date: 1st Edition, September 1997 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. |
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